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author | Seema Khowala <seemaj@nvidia.com> | 2017-03-01 16:43:40 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-30 19:39:11 -0400 |
commit | 7b5f1bd68d8e4b90d0d5d861dbea256d982c69e5 (patch) | |
tree | 2df281eba3dbb865397685c11d39258b90ca6537 /drivers/gpu/nvgpu/gv11b/mc_gv11b.c | |
parent | 3032acfc04f5c483dc08434f27f9912e7dee72c9 (diff) |
gpu: ngpu: gv11b: support hub interrupt
Hub interrupt handler will be added later
JIRA GPUT19X-7
Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313453
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/mc_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 83c03029..c901fd76 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c | |||
@@ -31,10 +31,12 @@ static void mc_gv11b_intr_enable(struct gk20a *g) | |||
31 | 0xffffffff); | 31 | 0xffffffff); |
32 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = | 32 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
33 | mc_intr_pfifo_pending_f() | | 33 | mc_intr_pfifo_pending_f() | |
34 | mc_intr_hub_pending_f() | | ||
34 | mc_intr_priv_ring_pending_f() | | 35 | mc_intr_priv_ring_pending_f() | |
35 | mc_intr_pbus_pending_f() | | 36 | mc_intr_pbus_pending_f() | |
36 | mc_intr_ltc_pending_f() | | 37 | mc_intr_ltc_pending_f() | |
37 | eng_intr_mask; | 38 | eng_intr_mask; |
39 | |||
38 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 40 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
39 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 41 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
40 | 42 | ||
@@ -47,8 +49,14 @@ static void mc_gv11b_intr_enable(struct gk20a *g) | |||
47 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 49 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |
48 | } | 50 | } |
49 | 51 | ||
52 | static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) | ||
53 | { | ||
54 | return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); | ||
55 | } | ||
56 | |||
50 | void gv11b_init_mc(struct gpu_ops *gops) | 57 | void gv11b_init_mc(struct gpu_ops *gops) |
51 | { | 58 | { |
52 | gp10b_init_mc(gops); | 59 | gp10b_init_mc(gops); |
53 | gops->mc.intr_enable = mc_gv11b_intr_enable; | 60 | gops->mc.intr_enable = mc_gv11b_intr_enable; |
61 | gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending; | ||
54 | } | 62 | } |