gpu: nvgpu: gv11b: detect stall intr during preemption

Check for interrupts or hangs while waiting for the preempt to complete.
During pbdma/eng preempt done polling, any stalling interrupts relating
to the runlist must be detected and handled in order for the preemption
to complete.

When PBDMA fault or CE fault occurs, the PBDMA will save out
automatically. TSG related to the context in which the fault occurred
will not be scheduled again until the fault is handled.
In the case of some other issue requiring the engine to be reset, TSG
will need to be manually preempted.

In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to
switch out. SW must handle these interrupts according to the relevant handling
procedure before the PBDMA preempt can complete.

Opt for eng reset instead of waiting for preemption to be finished when
there is any stall interrupt pending during engine context preempt completion.

Bug 200277163
Bug 1945121

Change-Id: Icaef79e3046d82987b8486d15cbfc8365aa26f2e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522914
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Tested-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 20 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index dab304e2..74c5c4d6 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -70,3 +70,23 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
 {
         return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false);
 }
+
+bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
+{
+        u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
+        u32 stall_intr, eng_intr_mask;
+
+        eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
+        if (mc_intr_0 & eng_intr_mask)
+                return true;
+
+        stall_intr = mc_intr_pfifo_pending_f() |
+                        mc_intr_hub_pending_f() |
+                        mc_intr_priv_ring_pending_f() |
+                        mc_intr_pbus_pending_f() |
+                        mc_intr_ltc_pending_f();
+        if (mc_intr_0 & stall_intr)
+                return true;
+
+        return false;
+}