gpu: nvgpu: gv11b: do not poll preempt done if eng intr pending

-During polling eng preempt done, reset eng only if eng stall
 intr is pending. Also stop polling for eng preempt done
 if eng intr is pending.
-Add max retries for pre-si platforms for poll pbdma and eng
 preempt done polling loops.

Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596

Change-Id: I66b07be9647f141bd03801f83e3cda797e88272f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694137
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 8 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 31600828..dbeb0645 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -71,24 +71,24 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
         return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false);
 }
 
-bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id)
+bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
+                        u32 *eng_intr_pending)
 {
         u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
         u32 stall_intr, eng_intr_mask;
 
         eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
-        if ((mc_intr_0 & eng_intr_mask) != 0U) {
-                return true;
-        }
+        *eng_intr_pending = mc_intr_0 & eng_intr_mask;
 
         stall_intr = mc_intr_pfifo_pending_f() |
                         mc_intr_hub_pending_f() |
                         mc_intr_priv_ring_pending_f() |
                         mc_intr_pbus_pending_f() |
                         mc_intr_ltc_pending_f();
-        if ((mc_intr_0 & stall_intr) != 0U) {
-                return true;
-        }
 
-        return false;
+        nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
+                "mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
+                mc_intr_0 & stall_intr, *eng_intr_pending);
+
+        return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
 }