gpu: nvgpu: gv11b: Support Stencil ZBC

Pre-GP10X
All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil
part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds).
Clears for these kinds typically happen in two phases, depth phase and
stencil phase. The depth clears can be compressed or ZBC-ed, whereas the
stencil part is always uncompressed.

Stencil ZBC in GP10X
For GP10X both the depth and the stencil data for these packed kinds can be
ZBC cleared. A given tile will be a cross product of the following states
for depth and stencil.
Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0,
ZBC index 1
Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2

JIRA GV11B-9

Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235520
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

1 files changed, 20 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
index df2b0f68..c0e46be3 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
@@ -1,7 +1,7 @@
 /*
  * GV11B LTC
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -20,7 +20,26 @@
 #include "gv11b/ltc_gv11b.h"
 #include "hw_ltc_gv11b.h"
 
+/*
+ * Sets the ZBC stencil for the passed index.
+ */
+static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
+                                          struct zbc_entry *stencil_val,
+                                          u32 index)
+{
+        u32 real_index = index + GK20A_STARTOF_ZBC_TABLE;
+
+        gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
+                     ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index));
+
+        gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
+                     stencil_val->depth);
+
+        gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r());
+}
+
 void gv11b_init_ltc(struct gpu_ops *gops)
 {
         gp10b_init_ltc(gops);
+        gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry;
 }