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| author | Lakshmanan M <lm@nvidia.com> | 2017-05-17 02:12:24 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-18 12:04:51 -0400 |
| commit | 5a08eafbe076fba98de62883636ee6b0751cf7e9 (patch) | |
| tree | 34d9406e93c5988b2dfe4a7ee7bbc042dd3a8507 /drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | |
| parent | d503a234440b0b5912f64314de68689b3211bbcd (diff) | |
gpu: nvgpu: gv11b: Add L1 DATA + iCACHE parity
This CL covers the following parity support (uncorrected error),
1) SM's L1 DATA
2) SM's L0 && L1 icache
Volta Resiliency Id - Volta-634
JIRA GPUT19X-113
JIRA GPUT19X-99
Bug 1807553
Change-Id: Iacbf492028983529dadc5753007e43510b8cb786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1483681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/ltc_gv11b.c')
0 files changed, 0 insertions, 0 deletions