gpu: nvgpu: gv11b: hw header update

Updated hw headers to CL#37001916. Some of
important changes include new door bell user
mode mechanism and new runlist structure.

Bug 1735765

Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1205888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
index 27ea4246..965f8663 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
@@ -608,11 +608,11 @@ static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
 }
 static inline u32 pwr_pmu_queue_head_r(u32 i)
 {
-        return 0x0010a4a0 + i*4;
+        return 0x0010a800 + i*4;
 }
 static inline u32 pwr_pmu_queue_head__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000008;
 }
 static inline u32 pwr_pmu_queue_head_address_f(u32 v)
 {
@@ -624,11 +624,11 @@ static inline u32 pwr_pmu_queue_head_address_v(u32 r)
 }
 static inline u32 pwr_pmu_queue_tail_r(u32 i)
 {
-        return 0x0010a4b0 + i*4;
+        return 0x0010a820 + i*4;
 }
 static inline u32 pwr_pmu_queue_tail__size_1_v(void)
 {
-        return 0x00000004;
+        return 0x00000008;
 }
 static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
 {