gpu: nvgpu: gv11b: Update elpg init seq for gv11b.

This updates register address/value pairs for
ELPG init sequence in GV11B.

Bug 200365505.

Change-Id: I62517c378c39f5025f797cf849f10e6b0eae27a8
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612642
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index bdf741d9..6a21eb2d 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -589,7 +589,7 @@ static const struct gpu_ops gv11b_ops = {
                 .elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
         },
         .pmu = {
-                .pmu_setup_elpg = gp10b_pmu_setup_elpg,
+                .pmu_setup_elpg = gv11b_pmu_setup_elpg,
                 .pmu_get_queue_head = pwr_pmu_queue_head_r,
                 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
                 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,