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authorSunny He <suhe@nvidia.com>2017-06-28 19:00:52 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-06 13:54:57 -0400
commitc9b92595b2ac50dbfc2f6e2f9998d469b5ab4fbe (patch)
tree93fca923c972ae1ea3e4c78135b96e53a753bed6 /drivers/gpu/nvgpu/gv11b/hal_gv11b.c
parentce308666f55cd4699c9e118cac291879ddc066ed (diff)
gpu: nvgpu: gv11b: Reorg misc HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I098559103ef280faca4e82708bb47b9b37057cfd Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510390 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c147
1 files changed, 76 insertions, 71 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 0e874c8a..98350e4b 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -52,75 +52,6 @@
52 52
53#include <nvgpu/hw/gv11b/hw_proj_gv11b.h> 53#include <nvgpu/hw/gv11b/hw_proj_gv11b.h>
54 54
55static const struct gpu_ops gv11b_ops = {
56 .ltc = {
57 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
58 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
59 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
60 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
61 .init_cbc = NULL,
62 .init_fs_state = gv11b_ltc_init_fs_state,
63 .init_comptags = gp10b_ltc_init_comptags,
64 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
65 .isr = gv11b_ltc_isr,
66 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
67 .flush = gm20b_flush_ltc,
68#ifdef CONFIG_DEBUG_FS
69 .sync_debugfs = gp10b_ltc_sync_debugfs,
70#endif
71 },
72 .clock_gating = {
73 .slcg_bus_load_gating_prod =
74 gv11b_slcg_bus_load_gating_prod,
75 .slcg_ce2_load_gating_prod =
76 gv11b_slcg_ce2_load_gating_prod,
77 .slcg_chiplet_load_gating_prod =
78 gv11b_slcg_chiplet_load_gating_prod,
79 .slcg_ctxsw_firmware_load_gating_prod =
80 gv11b_slcg_ctxsw_firmware_load_gating_prod,
81 .slcg_fb_load_gating_prod =
82 gv11b_slcg_fb_load_gating_prod,
83 .slcg_fifo_load_gating_prod =
84 gv11b_slcg_fifo_load_gating_prod,
85 .slcg_gr_load_gating_prod =
86 gr_gv11b_slcg_gr_load_gating_prod,
87 .slcg_ltc_load_gating_prod =
88 ltc_gv11b_slcg_ltc_load_gating_prod,
89 .slcg_perf_load_gating_prod =
90 gv11b_slcg_perf_load_gating_prod,
91 .slcg_priring_load_gating_prod =
92 gv11b_slcg_priring_load_gating_prod,
93 .slcg_pmu_load_gating_prod =
94 gv11b_slcg_pmu_load_gating_prod,
95 .slcg_therm_load_gating_prod =
96 gv11b_slcg_therm_load_gating_prod,
97 .slcg_xbar_load_gating_prod =
98 gv11b_slcg_xbar_load_gating_prod,
99 .blcg_bus_load_gating_prod =
100 gv11b_blcg_bus_load_gating_prod,
101 .blcg_ce_load_gating_prod =
102 gv11b_blcg_ce_load_gating_prod,
103 .blcg_ctxsw_firmware_load_gating_prod =
104 gv11b_blcg_ctxsw_firmware_load_gating_prod,
105 .blcg_fb_load_gating_prod =
106 gv11b_blcg_fb_load_gating_prod,
107 .blcg_fifo_load_gating_prod =
108 gv11b_blcg_fifo_load_gating_prod,
109 .blcg_gr_load_gating_prod =
110 gv11b_blcg_gr_load_gating_prod,
111 .blcg_ltc_load_gating_prod =
112 gv11b_blcg_ltc_load_gating_prod,
113 .blcg_pwr_csb_load_gating_prod =
114 gv11b_blcg_pwr_csb_load_gating_prod,
115 .blcg_pmu_load_gating_prod =
116 gv11b_blcg_pmu_load_gating_prod,
117 .blcg_xbar_load_gating_prod =
118 gv11b_blcg_xbar_load_gating_prod,
119 .pg_gr_load_gating_prod =
120 gr_gv11b_pg_gr_load_gating_prod,
121 }
122};
123
124static int gv11b_get_litter_value(struct gk20a *g, int value) 55static int gv11b_get_litter_value(struct gk20a *g, int value)
125{ 56{
126 int ret = EINVAL; 57 int ret = EINVAL;
@@ -202,6 +133,77 @@ static int gv11b_get_litter_value(struct gk20a *g, int value)
202 return ret; 133 return ret;
203} 134}
204 135
136static const struct gpu_ops gv11b_ops = {
137 .ltc = {
138 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
139 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
140 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
141 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
142 .init_cbc = NULL,
143 .init_fs_state = gv11b_ltc_init_fs_state,
144 .init_comptags = gp10b_ltc_init_comptags,
145 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
146 .isr = gv11b_ltc_isr,
147 .cbc_fix_config = gv11b_ltc_cbc_fix_config,
148 .flush = gm20b_flush_ltc,
149#ifdef CONFIG_DEBUG_FS
150 .sync_debugfs = gp10b_ltc_sync_debugfs,
151#endif
152 },
153 .clock_gating = {
154 .slcg_bus_load_gating_prod =
155 gv11b_slcg_bus_load_gating_prod,
156 .slcg_ce2_load_gating_prod =
157 gv11b_slcg_ce2_load_gating_prod,
158 .slcg_chiplet_load_gating_prod =
159 gv11b_slcg_chiplet_load_gating_prod,
160 .slcg_ctxsw_firmware_load_gating_prod =
161 gv11b_slcg_ctxsw_firmware_load_gating_prod,
162 .slcg_fb_load_gating_prod =
163 gv11b_slcg_fb_load_gating_prod,
164 .slcg_fifo_load_gating_prod =
165 gv11b_slcg_fifo_load_gating_prod,
166 .slcg_gr_load_gating_prod =
167 gr_gv11b_slcg_gr_load_gating_prod,
168 .slcg_ltc_load_gating_prod =
169 ltc_gv11b_slcg_ltc_load_gating_prod,
170 .slcg_perf_load_gating_prod =
171 gv11b_slcg_perf_load_gating_prod,
172 .slcg_priring_load_gating_prod =
173 gv11b_slcg_priring_load_gating_prod,
174 .slcg_pmu_load_gating_prod =
175 gv11b_slcg_pmu_load_gating_prod,
176 .slcg_therm_load_gating_prod =
177 gv11b_slcg_therm_load_gating_prod,
178 .slcg_xbar_load_gating_prod =
179 gv11b_slcg_xbar_load_gating_prod,
180 .blcg_bus_load_gating_prod =
181 gv11b_blcg_bus_load_gating_prod,
182 .blcg_ce_load_gating_prod =
183 gv11b_blcg_ce_load_gating_prod,
184 .blcg_ctxsw_firmware_load_gating_prod =
185 gv11b_blcg_ctxsw_firmware_load_gating_prod,
186 .blcg_fb_load_gating_prod =
187 gv11b_blcg_fb_load_gating_prod,
188 .blcg_fifo_load_gating_prod =
189 gv11b_blcg_fifo_load_gating_prod,
190 .blcg_gr_load_gating_prod =
191 gv11b_blcg_gr_load_gating_prod,
192 .blcg_ltc_load_gating_prod =
193 gv11b_blcg_ltc_load_gating_prod,
194 .blcg_pwr_csb_load_gating_prod =
195 gv11b_blcg_pwr_csb_load_gating_prod,
196 .blcg_pmu_load_gating_prod =
197 gv11b_blcg_pmu_load_gating_prod,
198 .blcg_xbar_load_gating_prod =
199 gv11b_blcg_xbar_load_gating_prod,
200 .pg_gr_load_gating_prod =
201 gr_gv11b_pg_gr_load_gating_prod,
202 },
203 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
204 .get_litter_value = gv11b_get_litter_value,
205};
206
205int gv11b_init_hal(struct gk20a *g) 207int gv11b_init_hal(struct gk20a *g)
206{ 208{
207 struct gpu_ops *gops = &g->ops; 209 struct gpu_ops *gops = &g->ops;
@@ -210,6 +212,11 @@ int gv11b_init_hal(struct gk20a *g)
210 gops->ltc = gv11b_ops.ltc; 212 gops->ltc = gv11b_ops.ltc;
211 gops->clock_gating = gv11b_ops.clock_gating; 213 gops->clock_gating = gv11b_ops.clock_gating;
212 214
215 /* Lone functions */
216 gops->chip_init_gpu_characteristics =
217 gv11b_ops.chip_init_gpu_characteristics;
218 gops->get_litter_value = gv11b_ops.get_litter_value;
219
213 /* boot in non-secure modes for time beeing */ 220 /* boot in non-secure modes for time beeing */
214 gops->privsecurity = 0; 221 gops->privsecurity = 0;
215 gops->securegpccs = 0; 222 gops->securegpccs = 0;
@@ -235,8 +242,6 @@ int gv11b_init_hal(struct gk20a *g)
235 gk20a_init_css_ops(gops); 242 gk20a_init_css_ops(gops);
236#endif 243#endif
237 g->name = "gv11b"; 244 g->name = "gv11b";
238 gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics;
239 gops->get_litter_value = gv11b_get_litter_value;
240 245
241 c->twod_class = FERMI_TWOD_A; 246 c->twod_class = FERMI_TWOD_A;
242 c->threed_class = VOLTA_A; 247 c->threed_class = VOLTA_A;
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