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authorDivya Singhatwaria <dsinghatwari@nvidia.com>2019-07-23 01:13:35 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2019-08-02 15:57:24 -0400
commitae175e45edc5807131dfb1b63d3e4795e96a3f86 (patch)
treec209caf5a5804f250be83e4a68295daa64d6cfb5 /drivers/gpu/nvgpu/gv11b/hal_gv11b.c
parent47f6bc0c2e85d0a8ff943b88c81108ca1bfc588e (diff)
gpu: nvgpu: Use TPC_PG_MASK to powergate the TPC
- In GV11B, read fuse_status_opt_tpc_gpc register to read which TPCs are floorswept. - The driver will also read sysfs node: tpc_pg_mask - Based on these two values "can_tpc_powergate" will be set to true or false and mask will be used to write to fuse_ctrl_opt_tpc_gpc register to powergate the TPC. - can_tpc_powergate = true indicates that the mask value sent from userspace is valid and can be used to power gate the desired TPC - can_tpc_powergate = false indicates that the mask value sent from userspace is not valid and cannot be used to power gate the desired TPC. Bug 200532639 Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2159219 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 6b4eeb88..2225e380 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -88,6 +88,7 @@
88#include "regops_gv11b.h" 88#include "regops_gv11b.h"
89#include "subctx_gv11b.h" 89#include "subctx_gv11b.h"
90#include "ecc_gv11b.h" 90#include "ecc_gv11b.h"
91#include "tpc_gv11b.h"
91 92
92#include <nvgpu/ptimer.h> 93#include <nvgpu/ptimer.h>
93#include <nvgpu/debug.h> 94#include <nvgpu/debug.h>
@@ -859,6 +860,9 @@ static const struct gpu_ops gv11b_ops = {
859 .acr = { 860 .acr = {
860 .acr_sw_init = nvgpu_gv11b_acr_sw_init, 861 .acr_sw_init = nvgpu_gv11b_acr_sw_init,
861 }, 862 },
863 .tpc = {
864 .tpc_powergate = gv11b_tpc_powergate,
865 },
862 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, 866 .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics,
863 .get_litter_value = gv11b_get_litter_value, 867 .get_litter_value = gv11b_get_litter_value,
864}; 868};
@@ -893,6 +897,7 @@ int gv11b_init_hal(struct gk20a *g)
893 gops->falcon = gv11b_ops.falcon; 897 gops->falcon = gv11b_ops.falcon;
894 gops->priv_ring = gv11b_ops.priv_ring; 898 gops->priv_ring = gv11b_ops.priv_ring;
895 gops->fuse = gv11b_ops.fuse; 899 gops->fuse = gv11b_ops.fuse;
900 gops->tpc = gv11b_ops.tpc;
896 gops->clk_arb = gv11b_ops.clk_arb; 901 gops->clk_arb = gv11b_ops.clk_arb;
897 gops->acr = gv11b_ops.acr; 902 gops->acr = gv11b_ops.acr;
898 903