gpu: nvgpu: handle misaligned_addr SM exception

We right now do not handle misaligned_addr SM exception explicitly and hence
we incorrectly initiate CILP on this exception

Handle this exception explicitly in this sequence -
- set error notifier first
- clear the interrupt
- return error from gr_gv11b_handle_warp_esr_error_misaligned_addr() so that
  RC recovery is triggered by gk20a_gr_isr()

Ensure that the error value is propagated back to gk20a_gr_isr() correctly

Use nvgpu_set_error_notifier_if_empty() to set error notifier since this will
prevent overwriting of error notifier value in case gk20a_gr_isr() also tries
to write to some error notifier value

Bug 200388475
Jira NVGPU-554

Change-Id: I84c4d202a8068e738567ccd344e05d9d5f6ad2f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686781
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 2d6dc9b0..dd4bd55a 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -534,7 +534,7 @@ static const struct gpu_ops gv11b_ops = {
                 .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout,
                 .channel_suspend = gk20a_channel_suspend,
                 .channel_resume = gk20a_channel_resume,
-                .set_error_notifier = nvgpu_set_error_notifier,
+                .set_error_notifier = nvgpu_set_error_notifier_if_empty,
                 .setup_sw = gk20a_init_fifo_setup_sw,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,