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authorSunny He <suhe@nvidia.com>2017-08-17 19:10:42 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-24 12:34:43 -0400
commit866165749a0b7b2e6b219bb26bffd69d790d97c5 (patch)
tree912f2df921d7a8964947efa9be6bec25cf0445d7 /drivers/gpu/nvgpu/gv11b/hal_gv11b.c
parentbcf556b640a3680522b03042574081abe0e17fef (diff)
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c153
1 files changed, 151 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 4b64d44d..0c5776f0 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -32,6 +32,7 @@
32#include "gk20a/regops_gk20a.h" 32#include "gk20a/regops_gk20a.h"
33#include "gk20a/fb_gk20a.h" 33#include "gk20a/fb_gk20a.h"
34#include "gk20a/pmu_gk20a.h" 34#include "gk20a/pmu_gk20a.h"
35#include "gk20a/gr_gk20a.h"
35 36
36#include "gm20b/ltc_gm20b.h" 37#include "gm20b/ltc_gm20b.h"
37#include "gm20b/gr_gm20b.h" 38#include "gm20b/gr_gm20b.h"
@@ -51,6 +52,7 @@
51#include "gp10b/fb_gp10b.h" 52#include "gp10b/fb_gp10b.h"
52#include "gp10b/mm_gp10b.h" 53#include "gp10b/mm_gp10b.h"
53#include "gp10b/pmu_gp10b.h" 54#include "gp10b/pmu_gp10b.h"
55#include "gp10b/gr_gp10b.h"
54 56
55#include "gp106/pmu_gp106.h" 57#include "gp106/pmu_gp106.h"
56 58
@@ -194,6 +196,150 @@ static const struct gpu_ops gv11b_ops = {
194 .isr_nonstall = gp10b_ce_nonstall_isr, 196 .isr_nonstall = gp10b_ce_nonstall_isr,
195 .get_num_pce = gv11b_ce_get_num_pce, 197 .get_num_pce = gv11b_ce_get_num_pce,
196 }, 198 },
199 .gr = {
200 .init_gpc_mmu = gr_gv11b_init_gpc_mmu,
201 .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults,
202 .cb_size_default = gr_gv11b_cb_size_default,
203 .calc_global_ctx_buffer_size =
204 gr_gv11b_calc_global_ctx_buffer_size,
205 .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb,
206 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
207 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
208 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
209 .handle_sw_method = gr_gv11b_handle_sw_method,
210 .set_alpha_circular_buffer_size =
211 gr_gv11b_set_alpha_circular_buffer_size,
212 .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size,
213 .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions,
214 .is_valid_class = gr_gv11b_is_valid_class,
215 .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class,
216 .is_valid_compute_class = gr_gv11b_is_valid_compute_class,
217 .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
218 .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
219 .init_fs_state = gr_gv11b_init_fs_state,
220 .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
221 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
222 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
223 .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask,
224 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
225 .free_channel_ctx = gk20a_free_channel_ctx,
226 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
227 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
228 .get_zcull_info = gr_gk20a_get_zcull_info,
229 .is_tpc_addr = gr_gm20b_is_tpc_addr,
230 .get_tpc_num = gr_gm20b_get_tpc_num,
231 .detect_sm_arch = gr_gv11b_detect_sm_arch,
232 .add_zbc_color = gr_gp10b_add_zbc_color,
233 .add_zbc_depth = gr_gp10b_add_zbc_depth,
234 .zbc_set_table = gk20a_gr_zbc_set_table,
235 .zbc_query_table = gr_gk20a_query_zbc,
236 .pmu_save_zbc = gk20a_pmu_save_zbc,
237 .add_zbc = gr_gk20a_add_zbc,
238 .pagepool_default_size = gr_gv11b_pagepool_default_size,
239 .init_ctx_state = gr_gp10b_init_ctx_state,
240 .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx,
241 .free_gr_ctx = gr_gp10b_free_gr_ctx,
242 .update_ctxsw_preemption_mode =
243 gr_gp10b_update_ctxsw_preemption_mode,
244 .dump_gr_regs = gr_gv11b_dump_gr_status_regs,
245 .update_pc_sampling = gr_gm20b_update_pc_sampling,
246 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
247 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
248 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
249 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
250 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
251 .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
252 .wait_empty = gr_gv11b_wait_empty,
253 .init_cyclestats = gr_gv11b_init_cyclestats,
254 .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,
255 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
256 .bpt_reg_info = gv11b_gr_bpt_reg_info,
257 .get_access_map = gr_gv11b_get_access_map,
258 .handle_fecs_error = gr_gv11b_handle_fecs_error,
259 .handle_sm_exception = gr_gk20a_handle_sm_exception,
260 .handle_tex_exception = gr_gv11b_handle_tex_exception,
261 .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions,
262 .enable_exceptions = gr_gv11b_enable_exceptions,
263 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
264 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
265 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
266 .record_sm_error_state = gv11b_gr_record_sm_error_state,
267 .update_sm_error_state = gv11b_gr_update_sm_error_state,
268 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
269 .suspend_contexts = gr_gp10b_suspend_contexts,
270 .resume_contexts = gr_gk20a_resume_contexts,
271 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
272 .fuse_override = gp10b_gr_fuse_override,
273 .init_sm_id_table = gr_gv11b_init_sm_id_table,
274 .load_smid_config = gr_gv11b_load_smid_config,
275 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
276 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
277 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
278 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
279 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
280 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
281 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
282 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
283 .commit_inst = gr_gv11b_commit_inst,
284 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
285 .write_pm_ptr = gr_gv11b_write_pm_ptr,
286 .init_elcg_mode = gr_gv11b_init_elcg_mode,
287 .load_tpc_mask = gr_gv11b_load_tpc_mask,
288 .inval_icache = gr_gk20a_inval_icache,
289 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
290 .wait_for_pause = gr_gk20a_wait_for_pause,
291 .resume_from_pause = gv11b_gr_resume_from_pause,
292 .clear_sm_errors = gr_gk20a_clear_sm_errors,
293 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
294 .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel,
295 .sm_debugger_attached = gv11b_gr_sm_debugger_attached,
296 .suspend_single_sm = gv11b_gr_suspend_single_sm,
297 .suspend_all_sms = gv11b_gr_suspend_all_sms,
298 .resume_single_sm = gv11b_gr_resume_single_sm,
299 .resume_all_sms = gv11b_gr_resume_all_sms,
300 .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr,
301 .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr,
302 .get_sm_no_lock_down_hww_global_esr_mask =
303 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask,
304 .lock_down_sm = gv11b_gr_lock_down_sm,
305 .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down,
306 .clear_sm_hww = gv11b_gr_clear_sm_hww,
307 .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf,
308 .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs,
309 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
310 .set_boosted_ctx = gr_gp10b_set_boosted_ctx,
311 .set_preemption_mode = gr_gp10b_set_preemption_mode,
312 .set_czf_bypass = NULL,
313 .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
314 .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
315 .init_preemption_state = NULL,
316 .update_boosted_ctx = gr_gp10b_update_boosted_ctx,
317 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
318 .create_gr_sysfs = gr_gv11b_create_sysfs,
319 .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
320 .is_etpc_addr = gv11b_gr_pri_is_etpc_addr,
321 .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table,
322 .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception,
323 .zbc_s_query_table = gr_gv11b_zbc_s_query_table,
324 .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl,
325 .restore_context_header = gv11b_restore_context_header,
326 .handle_gpc_gpcmmu_exception =
327 gr_gv11b_handle_gpc_gpcmmu_exception,
328 .add_zbc_type_s = gr_gv11b_add_zbc_type_s,
329 .get_egpc_base = gv11b_gr_get_egpc_base,
330 .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num,
331 .handle_gpc_gpccs_exception =
332 gr_gv11b_handle_gpc_gpccs_exception,
333 .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl,
334 .access_smpc_reg = gv11b_gr_access_smpc_reg,
335 .is_egpc_addr = gv11b_gr_pri_is_egpc_addr,
336 .add_zbc_s = gr_gv11b_add_zbc_stencil,
337 .handle_gcc_exception = gr_gv11b_handle_gcc_exception,
338 .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle,
339 .handle_tpc_sm_ecc_exception =
340 gr_gv11b_handle_tpc_sm_ecc_exception,
341 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
342 },
197 .fb = { 343 .fb = {
198 .reset = gv11b_fb_reset, 344 .reset = gv11b_fb_reset,
199 .init_hw = gk20a_fb_init_hw, 345 .init_hw = gk20a_fb_init_hw,
@@ -490,6 +636,7 @@ int gv11b_init_hal(struct gk20a *g)
490 636
491 gops->ltc = gv11b_ops.ltc; 637 gops->ltc = gv11b_ops.ltc;
492 gops->ce2 = gv11b_ops.ce2; 638 gops->ce2 = gv11b_ops.ce2;
639 gops->gr = gv11b_ops.gr;
493 gops->fb = gv11b_ops.fb; 640 gops->fb = gv11b_ops.fb;
494 gops->clock_gating = gv11b_ops.clock_gating; 641 gops->clock_gating = gv11b_ops.clock_gating;
495 gops->fifo = gv11b_ops.fifo; 642 gops->fifo = gv11b_ops.fifo;
@@ -541,6 +688,8 @@ int gv11b_init_hal(struct gk20a *g)
541 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; 688 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
542 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; 689 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
543 gops->pmu.is_priv_load = gp10b_is_priv_load; 690 gops->pmu.is_priv_load = gp10b_is_priv_load;
691
692 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
544 } else { 693 } else {
545 /* Inherit from gk20a */ 694 /* Inherit from gk20a */
546 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, 695 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
@@ -549,9 +698,9 @@ int gv11b_init_hal(struct gk20a *g)
549 gops->pmu.load_lsfalcon_ucode = NULL; 698 gops->pmu.load_lsfalcon_ucode = NULL;
550 gops->pmu.init_wpr_region = NULL; 699 gops->pmu.init_wpr_region = NULL;
551 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; 700 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
552 }
553 701
554 gv11b_init_gr(g); 702 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
703 }
555 704
556 gv11b_init_uncompressed_kind_map(); 705 gv11b_init_uncompressed_kind_map();
557 gv11b_init_kind_attr(); 706 gv11b_init_kind_attr();