diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-01-23 15:16:40 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-31 16:23:30 -0500 |
commit | 791ce6bd5480a8393c12be55e8afa459cb4dd1ff (patch) | |
tree | c34ed1f076bec31bfc5b87a7fa490eb28a2789d6 /drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |
parent | 9beefc45516097db2eabf2887ff66d3334ff9fde (diff) |
gpu: nvgpu: gv11b: enable more gr exceptions
-pd, scc, ds, ssync, mme and sked exceptions are
enabled. This will be useful for debugging
-Handle enabled interrupts
-Add gr ops to handle ssync hww. For legacy
chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr.
Since ssync hww is not enabled on legacy chips, added
ssync hww exception handling for volta only.
Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ec86d74c..91d80080 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -399,6 +399,7 @@ static const struct gpu_ops gv11b_ops = { | |||
399 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, | 399 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, |
400 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, | 400 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, |
401 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | 401 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, |
402 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, | ||
402 | }, | 403 | }, |
403 | .fb = { | 404 | .fb = { |
404 | .reset = gv11b_fb_reset, | 405 | .reset = gv11b_fb_reset, |