gpu: nvgpu: gv11b: add clock gating prod settings

JIRA GV11B-15

Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1266705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 54 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 3124f540..ccaa570c 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -34,12 +34,66 @@
 #include "gv11b/fb_gv11b.h"
 #include "gv11b/fifo_gv11b.h"
 #include "gv11b/hw_proj_gv11b.h"
+#include "gv11b/gv11b_gating_reglist.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gk20a/dbg_gpu_gk20a.h"
 
 static struct gpu_ops gv11b_ops;
 
+static struct gpu_ops gv11b_ops = {
+        .clock_gating = {
+                .slcg_bus_load_gating_prod =
+                        gv11b_slcg_bus_load_gating_prod,
+                .slcg_ce2_load_gating_prod =
+                        gv11b_slcg_ce2_load_gating_prod,
+                .slcg_chiplet_load_gating_prod =
+                        gv11b_slcg_chiplet_load_gating_prod,
+                .slcg_ctxsw_firmware_load_gating_prod =
+                        gv11b_slcg_ctxsw_firmware_load_gating_prod,
+                .slcg_fb_load_gating_prod =
+                        gv11b_slcg_fb_load_gating_prod,
+                .slcg_fifo_load_gating_prod =
+                        gv11b_slcg_fifo_load_gating_prod,
+                .slcg_gr_load_gating_prod =
+                        gr_gv11b_slcg_gr_load_gating_prod,
+                .slcg_ltc_load_gating_prod =
+                        ltc_gv11b_slcg_ltc_load_gating_prod,
+                .slcg_perf_load_gating_prod =
+                        gv11b_slcg_perf_load_gating_prod,
+                .slcg_priring_load_gating_prod =
+                        gv11b_slcg_priring_load_gating_prod,
+                .slcg_pmu_load_gating_prod =
+                        gv11b_slcg_pmu_load_gating_prod,
+                .slcg_therm_load_gating_prod =
+                        gv11b_slcg_therm_load_gating_prod,
+                .slcg_xbar_load_gating_prod =
+                        gv11b_slcg_xbar_load_gating_prod,
+                .blcg_bus_load_gating_prod =
+                        gv11b_blcg_bus_load_gating_prod,
+                .blcg_ce_load_gating_prod =
+                        gv11b_blcg_ce_load_gating_prod,
+                .blcg_ctxsw_firmware_load_gating_prod =
+                        gv11b_blcg_ctxsw_firmware_load_gating_prod,
+                .blcg_fb_load_gating_prod =
+                        gv11b_blcg_fb_load_gating_prod,
+                .blcg_fifo_load_gating_prod =
+                        gv11b_blcg_fifo_load_gating_prod,
+                .blcg_gr_load_gating_prod =
+                        gv11b_blcg_gr_load_gating_prod,
+                .blcg_ltc_load_gating_prod =
+                        gv11b_blcg_ltc_load_gating_prod,
+                .blcg_pwr_csb_load_gating_prod =
+                        gv11b_blcg_pwr_csb_load_gating_prod,
+                .blcg_pmu_load_gating_prod =
+                        gv11b_blcg_pmu_load_gating_prod,
+                .blcg_xbar_load_gating_prod =
+                        gv11b_blcg_xbar_load_gating_prod,
+                .pg_gr_load_gating_prod =
+                        gr_gv11b_pg_gr_load_gating_prod,
+        }
+};
+
 static int gv11b_get_litter_value(struct gk20a *g, int value)
 {
         int ret = EINVAL;