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| author | Philip Elcan <pelcan@nvidia.com> | 2018-08-23 14:45:19 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 20:47:25 -0400 |
| commit | 2d0149c9abd74fd6bb59e076cfd46f49097e5662 (patch) | |
| tree | 3d14929f7721440b777abfc150a35abbb1b03f36 /drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |
| parent | 74639b444251d7adc222400625eb59a3d53d0c0a (diff) | |
gpu: nvgpu: resolve MISRA 10.3 violations
MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.
This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.
JIRA NVGPU-647
Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
0 files changed, 0 insertions, 0 deletions