gpu: nvgpu: gv11b: PMU parity HWW ECC support

Adding support for ISR handling of ECC parity errors for PMU unit and setting
the initial IRQDST mask to deliver ECC interrupts to host in the non-stall
PMU irq path

JIRA: GPUT19X-83

Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611625
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 6a21eb2d..f6bdf6e5 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -611,6 +611,8 @@ static const struct gpu_ops gv11b_ops = {
                 .pmu_nsbootstrap = gv11b_pmu_bootstrap,
                 .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask,
                 .is_pmu_supported = gv11b_is_pmu_supported,
+                .get_irqdest = gv11b_pmu_get_irqdest,
+                .handle_ext_irq = gv11b_pmu_handle_ext_irq,
         },
         .regops = {
                 .get_global_whitelist_ranges =