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authorseshendra <sgadagottu@nvidia.com>2019-09-03 13:47:41 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2019-09-06 01:39:24 -0400
commit07ddc5aaad9a89a758cb5fe247c06d845b025e65 (patch)
treebee0c647e6e484d52c8f41971eb625c0f1db91f1 /drivers/gpu/nvgpu/gv11b/hal_gv11b.c
parentf57cf74d57718c672b1af8dd957cc8bd9ea3bb6c (diff)
gpu: nvgpu: Enabling/disabling FECS trace support
- To enable FECS trace support, nvgpu should set the MSB of the read pointer (MAILBOX1). - The ucode will check if the feature is enabled/disabled before writing a record into the circular buffer. If the feature is disabled, it will not write the record. - If the feature is enabled and the buffer is not allocated, HW will throw a page fault error. Bug 2459186 Bug 200542611 Change-Id: I6f181643737d1cf1bda02077eaa714a3f4ef3d8c Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2189250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index ea9b41d8..84469fa0 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B Tegra HAL interface 2 * GV11B Tegra HAL interface
3 * 3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -949,6 +949,7 @@ int gv11b_init_hal(struct gk20a *g)
949 949
950 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); 950 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
951 __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); 951 __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
952 __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true);
952 953
953 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); 954 __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false);
954 955