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| author | David Nieto <dmartineznie@nvidia.com> | 2017-12-05 18:20:18 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-11 19:42:01 -0500 |
| commit | 258ae4471296bcee03987778e3b7c79d3a027e53 (patch) | |
| tree | a4890fa3a54b1857ba5c6ff3d770f84733b95154 /drivers/gpu/nvgpu/gv11b/gv11b.h | |
| parent | ba69628aafefcf4567f2f3b1459ccc4ebd8e203f (diff) | |
gpu: nvgpu: gv11b: PMU parity HWW ECC support
Adding support for ISR handling of ECC parity errors for PMU unit and setting
the initial IRQDST mask to deliver ECC interrupts to host in the non-stall
PMU irq path
JIRA: GPUT19X-83
Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611625
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gv11b.h')
0 files changed, 0 insertions, 0 deletions