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authorVinod G <vinodg@nvidia.com>2018-07-10 19:13:03 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-19 03:06:43 -0400
commitd859c5f4a03b975dc493f72a35016e83adad279a (patch)
treee7a1242a1d130a726456cf3a928a34941aad98f4 /drivers/gpu/nvgpu/gv11b/gv11b.c
parent74e1a11d840b3d7411b380c2e4e4c99126ea32a5 (diff)
nvgpu: gv11b: Rearrange gr function
Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gv11b.c121
1 files changed, 0 insertions, 121 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c
index 44120498..5d2bfbd7 100644
--- a/drivers/gpu/nvgpu/gv11b/gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gv11b.c
@@ -25,128 +25,7 @@
25#include <nvgpu/enabled.h> 25#include <nvgpu/enabled.h>
26 26
27#include "gk20a/gk20a.h" 27#include "gk20a/gk20a.h"
28#include "gp10b/gp10b.h"
29
30#include "gv11b/gv11b.h" 28#include "gv11b/gv11b.h"
31#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
32#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
33
34void gv11b_detect_ecc_enabled_units(struct gk20a *g)
35{
36 u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
37 u32 opt_feature_fuses_override_disable =
38 gk20a_readl(g,
39 fuse_opt_feature_fuses_override_disable_r());
40 u32 fecs_feature_override_ecc =
41 gk20a_readl(g,
42 gr_fecs_feature_override_ecc_r());
43
44 if (opt_feature_fuses_override_disable) {
45 if (opt_ecc_en) {
46 __nvgpu_set_enabled(g,
47 NVGPU_ECC_ENABLED_SM_LRF, true);
48 __nvgpu_set_enabled(g,
49 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
50 __nvgpu_set_enabled(g,
51 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
52 __nvgpu_set_enabled(g,
53 NVGPU_ECC_ENABLED_SM_ICACHE, true);
54 __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
55 __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true);
56 }
57 } else {
58 /* SM LRF */
59 if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
60 fecs_feature_override_ecc)) {
61 if (gr_fecs_feature_override_ecc_sm_lrf_v(
62 fecs_feature_override_ecc)) {
63 __nvgpu_set_enabled(g,
64 NVGPU_ECC_ENABLED_SM_LRF, true);
65 }
66 } else {
67 if (opt_ecc_en) {
68 __nvgpu_set_enabled(g,
69 NVGPU_ECC_ENABLED_SM_LRF, true);
70 }
71 }
72 /* SM L1 DATA*/
73 if (gr_fecs_feature_override_ecc_sm_l1_data_override_v(
74 fecs_feature_override_ecc)) {
75 if (gr_fecs_feature_override_ecc_sm_l1_data_v(
76 fecs_feature_override_ecc)) {
77 __nvgpu_set_enabled(g,
78 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
79 }
80 } else {
81 if (opt_ecc_en) {
82 __nvgpu_set_enabled(g,
83 NVGPU_ECC_ENABLED_SM_L1_DATA, true);
84 }
85 }
86 /* SM L1 TAG*/
87 if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v(
88 fecs_feature_override_ecc)) {
89 if (gr_fecs_feature_override_ecc_sm_l1_tag_v(
90 fecs_feature_override_ecc)) {
91 __nvgpu_set_enabled(g,
92 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
93 }
94 } else {
95 if (opt_ecc_en) {
96 __nvgpu_set_enabled(g,
97 NVGPU_ECC_ENABLED_SM_L1_TAG, true);
98 }
99 }
100 /* SM ICACHE*/
101 if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(
102 fecs_feature_override_ecc) &&
103 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(
104 fecs_feature_override_ecc)) {
105 if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v(
106 fecs_feature_override_ecc) &&
107 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(
108 fecs_feature_override_ecc)) {
109 __nvgpu_set_enabled(g,
110 NVGPU_ECC_ENABLED_SM_ICACHE, true);
111 }
112 } else {
113 if (opt_ecc_en) {
114 __nvgpu_set_enabled(g,
115 NVGPU_ECC_ENABLED_SM_ICACHE, true);
116 }
117 }
118 /* LTC */
119 if (gr_fecs_feature_override_ecc_ltc_override_v(
120 fecs_feature_override_ecc)) {
121 if (gr_fecs_feature_override_ecc_ltc_v(
122 fecs_feature_override_ecc)) {
123 __nvgpu_set_enabled(g,
124 NVGPU_ECC_ENABLED_LTC, true);
125 }
126 } else {
127 if (opt_ecc_en) {
128 __nvgpu_set_enabled(g,
129 NVGPU_ECC_ENABLED_LTC, true);
130 }
131 }
132 /* SM CBU */
133 if (gr_fecs_feature_override_ecc_sm_cbu_override_v(
134 fecs_feature_override_ecc)) {
135 if (gr_fecs_feature_override_ecc_sm_cbu_v(
136 fecs_feature_override_ecc)) {
137 __nvgpu_set_enabled(g,
138 NVGPU_ECC_ENABLED_SM_CBU, true);
139 }
140 } else {
141 if (opt_ecc_en) {
142 __nvgpu_set_enabled(g,
143 NVGPU_ECC_ENABLED_SM_CBU, true);
144 }
145 }
146 }
147}
148
149
150 29
151int gv11b_init_gpu_characteristics(struct gk20a *g) 30int gv11b_init_gpu_characteristics(struct gk20a *g)
152{ 31{
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