diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-08 20:20:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-13 01:15:19 -0400 |
commit | df022d27ddf2f66bff04170bb454fa26db8d51b1 (patch) | |
tree | 84f69276f8615330068519b2979b081324fc0484 /drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |
parent | 66fb130bfdf12175c117f36737503b1b5f33d42e (diff) |
gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methods
Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK
data fields are
data:0 SKEDCHECK_18_DISABLE
data:1 SKEDCHECK_18_ENABLE
Bug 200315442
Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515772
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index ff5782d9..1e060bd0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -40,11 +40,19 @@ enum { | |||
40 | #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc | 40 | #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc |
41 | #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c | 41 | #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c |
42 | #define NVC397_SET_TEX_IN_DBG 0x10bc | 42 | #define NVC397_SET_TEX_IN_DBG 0x10bc |
43 | #define NVC397_SET_SKEDCHECK 0x10c0 | ||
43 | 44 | ||
44 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 | 45 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 |
45 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 | 46 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 |
46 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 | 47 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 |
47 | 48 | ||
49 | #define NVC397_SET_SKEDCHECK_18_MASK 0x3 | ||
50 | #define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0 | ||
51 | #define NVC397_SET_SKEDCHECK_18_DISABLE 0x1 | ||
52 | #define NVC397_SET_SKEDCHECK_18_ENABLE 0x2 | ||
53 | |||
54 | #define NVC3C0_SET_SKEDCHECK 0x23c | ||
55 | |||
48 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 56 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
49 | 57 | ||
50 | void gv11b_init_gr(struct gpu_ops *ops); | 58 | void gv11b_init_gr(struct gpu_ops *ops); |