diff options
author | Vinod G <vinodg@nvidia.com> | 2018-08-08 02:09:30 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-25 05:10:43 -0400 |
commit | bfe65407bde2b5d0776724301e215c6553c989f3 (patch) | |
tree | f68a01361052afe1c30a0c6dcd5d359b762e647a /drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |
parent | 3bd47da0954d3486d9ccd3c396f84445918f82b4 (diff) |
gpu: nvgpu: Read sm error ioctl support for tsg
Add READ_SM_ERROR IOCTL support to TSG level.
Moved the struct to save the sm_error details
from gr to tsg as the sm_error support is context
based, not global.
Also corrected MISRA 21.1 error in header file.
nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and
nvgpu_dbg_gpu_ioctl_read_single_sm_error_state
functions are modified to use the tsg struct
nvgpu_tsg_sm_error_state.
Bug 200412642
Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794856
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 0f29ea24..30cc7f0a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -43,7 +43,7 @@ struct zbc_entry; | |||
43 | struct zbc_query_params; | 43 | struct zbc_query_params; |
44 | struct nvgpu_gr_ctx; | 44 | struct nvgpu_gr_ctx; |
45 | struct nvgpu_warpstate; | 45 | struct nvgpu_warpstate; |
46 | struct nvgpu_gr_sm_error_state; | 46 | struct nvgpu_tsg_sm_error_state; |
47 | struct gr_ctx_desc; | 47 | struct gr_ctx_desc; |
48 | struct gr_gk20a_isr_data; | 48 | struct gr_gk20a_isr_data; |
49 | struct gk20a_debug_output; | 49 | struct gk20a_debug_output; |
@@ -168,7 +168,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g); | |||
168 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); | 168 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); |
169 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | 169 | int gv11b_gr_update_sm_error_state(struct gk20a *g, |
170 | struct channel_gk20a *ch, u32 sm_id, | 170 | struct channel_gk20a *ch, u32 sm_id, |
171 | struct nvgpu_gr_sm_error_state *sm_error_state); | 171 | struct nvgpu_tsg_sm_error_state *sm_error_state); |
172 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 172 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
173 | struct channel_gk20a *ch, u64 sms, bool enable); | 173 | struct channel_gk20a *ch, u64 sms, bool enable); |
174 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 174 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |