gpu: nvgpu: gv11b: Support Stencil ZBC

Pre-GP10X
All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil
part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds).
Clears for these kinds typically happen in two phases, depth phase and
stencil phase. The depth clears can be compressed or ZBC-ed, whereas the
stencil part is always uncompressed.

Stencil ZBC in GP10X
For GP10X both the depth and the stencil data for these packed kinds can be
ZBC cleared. A given tile will be a cross product of the following states
for depth and stencil.
Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0,
ZBC index 1
Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2

JIRA GV11B-9

Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235520
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

1 files changed, 11 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index fe5445d9..d31c92ca 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -1,7 +1,7 @@
 /*
  * GV11B GPU GR
  *
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,6 +16,16 @@
 #ifndef _NVGPU_GR_GV11B_H_
 #define _NVGPU_GR_GV11B_H_
 
+#define GV11B_ZBC_TYPE_STENCIL            T19X_ZBC
+#define ZBC_STENCIL_CLEAR_FMT_INVAILD     0
+#define ZBC_STENCIL_CLEAR_FMT_U8          1
+
+struct zbc_s_table {
+        u32 stencil;
+        u32 format;
+        u32 ref_cnt;
+};
+
 struct gpu_ops;
 
 enum {