gpu: nvgpu: Add gv11b_gr_clear_sm_error_state

All chips were currently using gm20b_gr_clear_sm_error_state
It was wrong for chips based on volta and later as the implementation didn't
consider non pes-aware vsms mapping

Add new HAL implementation for clear_sm_error_state for volta based and later
chips to fix this.

Bug 200448172

Change-Id: I65988c8cbb35d13089ac628e8333d9a3b58e0eb1
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 20377acf..2f765336 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -170,6 +170,8 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
         struct channel_gk20a *ch, u64 sms, bool enable);
 int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                 struct channel_gk20a *fault_ch);
+int gv11b_gr_clear_sm_error_state(struct gk20a *g,
+                struct channel_gk20a *ch, u32 sm_id);
 void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g);
 bool gv11b_gr_sm_debugger_attached(struct gk20a *g);
 void gv11b_gr_suspend_single_sm(struct gk20a *g,