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authorseshendra Gadagottu <sgadagottu@nvidia.com>2018-01-02 18:48:46 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-10 11:47:03 -0500
commit0ac3ba2a99b745f577c752ebf9a6b4291730a36d (patch)
treedd111702d91dd5d14369def5fc152960f90a2daf /drivers/gpu/nvgpu/gv11b/gr_gv11b.h
parent3e9aa581b61a3ecbcf01a8988b1d12a8af8e2a45 (diff)
gpu: nvgpu: gv11b: fix for gfx preemption
Used chip specific attrib_cb_gfxp_default_size and attrib_cb_gfxp_size buffer sizes during committing global callback buffer when gfx preemption is requested. These sizes are different for gv11b from gp10b. For gp10b used smaller buffer sizes than specified value in hw manuals as per sw requirement. Also used gv11b specific preemption related functions: gr_gv11b_set_ctxsw_preemption_mode gr_gv11b_update_ctxsw_preemption_mode This is required because preemption related buffer sizes are different for gv11b from gp10b. More optimization will be done as part of NVGPU-484. Another issue fixed is: gpu va for preemption buffers still needs to be 8 bit aligned, even though 49 bits available now. This done because of legacy implementation of fecs ucode. Bug 1976694 Change-Id: I2dc923340d34d0dc5fe45419200d0cf4f53cdb23 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635027 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h13
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 39d12b3f..17e5e9e3 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B GPU GR 2 * GV11B GPU GR
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -46,6 +46,7 @@ struct zbc_query_params;
46struct channel_ctx_gk20a; 46struct channel_ctx_gk20a;
47struct nvgpu_warpstate; 47struct nvgpu_warpstate;
48struct nvgpu_gr_sm_error_state; 48struct nvgpu_gr_sm_error_state;
49struct gr_ctx_desc;
49struct gr_gk20a_isr_data; 50struct gr_gk20a_isr_data;
50struct gk20a_debug_output; 51struct gk20a_debug_output;
51 52
@@ -218,4 +219,14 @@ void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g);
218unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g); 219unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
219void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g); 220void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g);
220 221
222int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g,
223 struct gr_ctx_desc *gr_ctx,
224 struct vm_gk20a *vm, u32 class,
225 u32 graphics_preempt_mode,
226 u32 compute_preempt_mode);
227
228void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
229 struct channel_ctx_gk20a *ch_ctx,
230 struct nvgpu_mem *mem);
231
221#endif 232#endif