gpu: nvgpu: tpc powergating through sysfs

- adds static tpc-powergating through sysfs.
- active tpc count will remain till the GPU/systems is not booted again.
- tpc_pg_mask can be written only after GPU probe finishes and
  GPU boot is triggered.

Note:
To be able to use this feature, we need to change boot/init
scripts of the OS(used with nvgpu driver) to write to sysfs nodes before
posting discover image size query to FECS.

Bug 200406784

Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742422
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 40 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index c2f47a20..51588f1f 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -58,6 +58,7 @@
 #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
 
 #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 100
 
@@ -71,6 +72,16 @@
  */
 #define GR_TPCS_INFO_FOR_MAPREGISTER 6
 
+/*
+ * There are 4 TPCs in GV11b ranging from TPC0 to TPC3
+ * There are two PES in GV11b each controlling two TPCs
+ * PES0 is linked to TPC0 & TPC2
+ * PES1 is linked to TPC1 & TPC3
+ */
+#define TPC_MASK_FOR_PESID_0   (u32) 0x5
+#define TPC_MASK_FOR_PESID_1   (u32) 0xa
+
+
 bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num)
 {
         bool valid = false;
@@ -117,6 +128,35 @@ bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
         return valid;
 }
 
+void gr_gv11b_powergate_tpc(struct gk20a *g)
+{
+        u32 tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0));
+
+        if (tpc_pg_status == g->tpc_pg_mask) {
+                nvgpu_info(g, "TPC-PG mask and TPC-PG status is same");
+                return;
+        }
+
+        gk20a_writel(g, fuse_ctrl_opt_tpc_gpc_r(0), (g->tpc_pg_mask));
+
+        do {
+                tpc_pg_status = gk20a_readl(g, fuse_status_opt_tpc_gpc_r(0));
+        } while (tpc_pg_status != g->tpc_pg_mask);
+
+        gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() |
+                        gr_fe_tpc_pesmask_action_write_f() |
+                        gr_fe_tpc_pesmask_pesid_f(0) |
+                        gr_fe_tpc_pesmask_gpcid_f(0) |
+                        ((~g->tpc_pg_mask & (u32) 0xf) & TPC_MASK_FOR_PESID_0));
+        gk20a_writel(g, gr_fe_tpc_pesmask_r(), gr_fe_tpc_pesmask_req_send_f() |
+                        gr_fe_tpc_pesmask_action_write_f() |
+                        gr_fe_tpc_pesmask_pesid_f(1) |
+                        gr_fe_tpc_pesmask_gpcid_f(0) |
+                        ((~g->tpc_pg_mask & (u32) 0xf) & TPC_MASK_FOR_PESID_1));
+
+        return;
+}
+
 bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num)
 {
         bool valid = false;