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authorseshendra Gadagottu <sgadagottu@nvidia.com>2017-03-03 17:31:39 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-14 14:46:46 -0400
commita29521e8d84241ea27b83f14f80547a2da601a97 (patch)
tree4f55fb0c7ccd2a38895c289e771fd908df81dea1 /drivers/gpu/nvgpu/gv11b/gr_gv11b.c
parent679086c42ea58ce3c355e1dd8c17f662f84a2faf (diff)
gpu: nvgpu: gv11b: add tpc floor sweeping code
Added TPC floor sweeping code for gv11b. JIRA GV11B-73 Change-Id: Ib0d05e2d606fe13dff119948fbc9022e8af0fa7f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1315257 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c27
1 files changed, 26 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index c512322b..fabc6819 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2007,7 +2007,32 @@ void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
2007 2007
2008static void gr_gv11b_load_tpc_mask(struct gk20a *g) 2008static void gr_gv11b_load_tpc_mask(struct gk20a *g)
2009{ 2009{
2010 /* TODO */ 2010 u32 pes_tpc_mask = 0, fuse_tpc_mask;
2011 u32 gpc, pes, val;
2012 u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
2013 GPU_LIT_NUM_TPC_PER_GPC);
2014
2015 /* gv11b has 1 GPC and 4 TPC/GPC, so mask will not overflow u32 */
2016 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
2017 for (pes = 0; pes < g->gr.pe_count_per_gpc; pes++) {
2018 pes_tpc_mask |= g->gr.pes_tpc_mask[pes][gpc] <<
2019 num_tpc_per_gpc * gpc;
2020 }
2021 }
2022
2023 gk20a_dbg_info("pes_tpc_mask %u\n", pes_tpc_mask);
2024 fuse_tpc_mask = g->ops.gr.get_gpc_tpc_mask(g, gpc);
2025 if (g->tpc_fs_mask_user &&
2026 g->tpc_fs_mask_user != fuse_tpc_mask &&
2027 fuse_tpc_mask == (0x1U << g->gr.max_tpc_count) - 1U) {
2028 val = g->tpc_fs_mask_user;
2029 val &= (0x1U << g->gr.max_tpc_count) - 1U;
2030 val = (0x1U << hweight32(val)) - 1U;
2031 gk20a_writel(g, gr_fe_tpc_fs_r(0), val);
2032 } else {
2033 gk20a_writel(g, gr_fe_tpc_fs_r(0), pes_tpc_mask);
2034 }
2035
2011} 2036}
2012 2037
2013void gv11b_init_gr(struct gpu_ops *gops) 2038void gv11b_init_gr(struct gpu_ops *gops)