gpu: nvgpu: gv100: consider floorswept FBPA for getting unicast list

In gr_gv11b/gk20a_create_priv_addr_table() we do not consider floorswept FBPAs
and just calculate the unicast list assuming all FBPAs are present
This generates incorrect list of unicast addresses

Fix this introducing new HAL ops.gr.split_fbpa_broadcast_addr
Set gr_gv100_get_active_fpba_mask() for GV100
Set gr_gk20a_split_fbpa_broadcast_addr() for rest of the chips

gr_gv100_get_active_fpba_mask() will first get active FPBA mask and generate
unicast list only for active FBPAs

Bug 200398811
Jira NVGPU-556

Change-Id: Idd11d6e7ad7b6836525fe41509aeccf52038321f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694444
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index dfb14db7..24366911 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4557,7 +4557,6 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
         u32 broadcast_flags;
         u32 t;
         int err;
-        int fbpa_num;
 
         t = 0;
         *num_registers = 0;
@@ -4671,11 +4670,9 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                 g->ops.gr.split_ltc_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_FBPA) {
-                for (fbpa_num = 0;
-                     fbpa_num < nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS);
-                     fbpa_num++)
-                        priv_addr_table[t++] = pri_fbpa_addr(g,
-                                        pri_fbpa_addr_mask(g, addr), fbpa_num);
+                g->ops.gr.split_fbpa_broadcast_addr(g, addr,
+                                nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS),
+                                priv_addr_table, &t);
         } else if ((addr_type == CTXSW_ADDR_TYPE_LTCS) &&
                    (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC)) {
                 gr_gv11b_split_pmm_fbp_broadcast_address(g,