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authorseshendra Gadagottu <sgadagottu@nvidia.com>2018-03-26 21:23:52 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-24 07:35:53 -0400
commit9ae69536b997db1ffa5ef81599a73e164efe8b9d (patch)
treef89e8dfe1f638302581f2d46e8ab215aad0cad3f /drivers/gpu/nvgpu/gv11b/gr_gv11b.c
parent67c4571d959ec1066cbacb7f9ff1c19ea5fdd079 (diff)
gpu: nvgpu: gv11b: chip revision check for invalidates
Only for T194 A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 536d9dcb..df323da1 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -31,6 +31,7 @@
31#include <nvgpu/fuse.h> 31#include <nvgpu/fuse.h>
32#include <nvgpu/bug.h> 32#include <nvgpu/bug.h>
33#include <nvgpu/error_notifier.h> 33#include <nvgpu/error_notifier.h>
34#include <nvgpu/soc.h>
34 35
35#include "gk20a/gk20a.h" 36#include "gk20a/gk20a.h"
36#include "gk20a/gr_gk20a.h" 37#include "gk20a/gr_gk20a.h"
@@ -2860,7 +2861,6 @@ int gr_gv11b_init_fs_state(struct gk20a *g)
2860 u32 data; 2861 u32 data;
2861 int err; 2862 int err;
2862 u32 ver = g->params.gpu_arch + g->params.gpu_impl; 2863 u32 ver = g->params.gpu_arch + g->params.gpu_impl;
2863 u32 rev = g->params.gpu_rev;
2864 2864
2865 nvgpu_log_fn(g, " "); 2865 nvgpu_log_fn(g, " ");
2866 2866
@@ -2869,9 +2869,9 @@ int gr_gv11b_init_fs_state(struct gk20a *g)
2869 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); 2869 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
2870 gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); 2870 gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
2871 2871
2872 if (ver == NVGPU_GPUID_GV11B && rev == 0xa1) { 2872 if (ver == NVGPU_GPUID_GV11B && nvgpu_is_soc_t194_a01(g))
2873 2873 {
2874 /* Disable CBM alpha and beta invalidations for l2 for gv11b A01 */ 2874 /* Disable CBM alpha and beta invalidations for l2 for t194 A01 */
2875 data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r()); 2875 data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r());
2876 data = set_field(data, 2876 data = set_field(data,
2877 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(), 2877 gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(),
@@ -2881,14 +2881,14 @@ int gr_gv11b_init_fs_state(struct gk20a *g)
2881 gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f()); 2881 gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f());
2882 gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data); 2882 gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data);
2883 2883
2884 /* Disable SCC pagepool invalidates for gv11b A01 */ 2884 /* Disable SCC pagepool invalidates for t194 A01 */
2885 data = gk20a_readl(g, gr_scc_debug_r()); 2885 data = gk20a_readl(g, gr_scc_debug_r());
2886 data = set_field(data, 2886 data = set_field(data,
2887 gr_scc_debug_pagepool_invalidates_m(), 2887 gr_scc_debug_pagepool_invalidates_m(),
2888 gr_scc_debug_pagepool_invalidates_disable_f()); 2888 gr_scc_debug_pagepool_invalidates_disable_f());
2889 gk20a_writel(g, gr_scc_debug_r(), data); 2889 gk20a_writel(g, gr_scc_debug_r(), data);
2890 2890
2891 /* Disable SWDX spill buffer invalidates for gv11b A01 */ 2891 /* Disable SWDX spill buffer invalidates */
2892 data = gk20a_readl(g, gr_gpcs_swdx_spill_unit_r()); 2892 data = gk20a_readl(g, gr_gpcs_swdx_spill_unit_r());
2893 data = set_field(data, 2893 data = set_field(data,
2894 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(), 2894 gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(),