gpu: nvgpu: use hard coded tpc count mask

In gr_gv11b_set_gpc_tpc_mask(), we calculate tpc_count_mask based on
number of TPCs
But since we could change number of TPCs runtime, we would end up
calulating incorrect tpc_count_mask

Hence instead of calculating tpc_count_mask, just hard code it to
width of fuse register i.e. hard code tpc_count_mask to 4-bit value

Bug 2031635

Change-Id: Ia6f74d39d066775a5d133897305554df1e54157e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617917
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 2b242978..fe0584f6 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1688,7 +1688,6 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
 
 void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-        u32 tpc_count_mask;
         u32 fuse_val;
 
         if (!g->gr.gpc_tpc_mask[gpc_index])
@@ -1701,11 +1700,9 @@ void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
          * So we need to flip the bits and ensure we don't write to bits greater
          * than TPC count
          */
-        tpc_count_mask = (1 << gr_gk20a_get_tpc_count(&g->gr, gpc_index)) - 1;
-
         fuse_val = g->gr.gpc_tpc_mask[gpc_index];
         fuse_val = ~fuse_val;
-        fuse_val = fuse_val & tpc_count_mask;
+        fuse_val = fuse_val & 0xf; /* tpc0_disable fuse is only 4-bit wide */
 
         nvgpu_tegra_fuse_write_bypass(g, 0x1);
         nvgpu_tegra_fuse_write_access_sw(g, 0x0);