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authorSunny He <suhe@nvidia.com>2017-08-17 19:10:42 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-24 12:34:43 -0400
commit866165749a0b7b2e6b219bb26bffd69d790d97c5 (patch)
tree912f2df921d7a8964947efa9be6bec25cf0445d7 /drivers/gpu/nvgpu/gv11b/gr_gv11b.c
parentbcf556b640a3680522b03042574081abe0e17fef (diff)
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c259
1 files changed, 79 insertions, 180 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 2b0e8be7..078272d1 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -51,7 +51,7 @@
51#include <nvgpu/hw/gv11b/hw_therm_gv11b.h> 51#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
52#include <nvgpu/hw/gv11b/hw_fb_gv11b.h> 52#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
53 53
54static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) 54bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num)
55{ 55{
56 bool valid = false; 56 bool valid = false;
57 57
@@ -80,7 +80,7 @@ static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num)
80 return valid; 80 return valid;
81} 81}
82 82
83static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) 83bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
84{ 84{
85 bool valid = false; 85 bool valid = false;
86 86
@@ -97,7 +97,7 @@ static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
97 return valid; 97 return valid;
98} 98}
99 99
100static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) 100bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num)
101{ 101{
102 bool valid = false; 102 bool valid = false;
103 103
@@ -299,7 +299,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
299 299
300} 300}
301 301
302static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) 302void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
303{ 303{
304 /* enable exceptions */ 304 /* enable exceptions */
305 gk20a_writel(g, gr_fe_hww_esr_r(), 305 gk20a_writel(g, gr_fe_hww_esr_r(),
@@ -310,7 +310,7 @@ static void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
310 gr_memfmt_hww_esr_reset_active_f()); 310 gr_memfmt_hww_esr_reset_active_f());
311} 311}
312 312
313static void gr_gv11b_enable_exceptions(struct gk20a *g) 313void gr_gv11b_enable_exceptions(struct gk20a *g)
314{ 314{
315 struct gr_gk20a *gr = &g->gr; 315 struct gr_gk20a *gr = &g->gr;
316 u32 reg_val; 316 u32 reg_val;
@@ -581,7 +581,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc,
581 581
582} 582}
583 583
584static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, 584int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
585 u32 gpc, u32 tpc, 585 u32 gpc, u32 tpc,
586 bool *post_event, struct channel_gk20a *fault_ch, 586 bool *post_event, struct channel_gk20a *fault_ch,
587 u32 *hww_global_esr) 587 u32 *hww_global_esr)
@@ -606,7 +606,7 @@ static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
606 return ret; 606 return ret;
607} 607}
608 608
609static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, 609int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc,
610 bool *post_event, struct channel_gk20a *fault_ch, 610 bool *post_event, struct channel_gk20a *fault_ch,
611 u32 *hww_global_esr) 611 u32 *hww_global_esr)
612{ 612{
@@ -852,7 +852,7 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc,
852 return ret; 852 return ret;
853} 853}
854 854
855static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, 855int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
856 u32 gpc_exception) 856 u32 gpc_exception)
857{ 857{
858 if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) 858 if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m())
@@ -861,7 +861,7 @@ static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc,
861 return 0; 861 return 0;
862} 862}
863 863
864static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, 864int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc,
865 u32 gpc_exception) 865 u32 gpc_exception)
866{ 866{
867 if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) 867 if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m())
@@ -871,7 +871,7 @@ static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc,
871 return 0; 871 return 0;
872} 872}
873 873
874static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) 874void gr_gv11b_enable_gpc_exceptions(struct gk20a *g)
875{ 875{
876 struct gr_gk20a *gr = &g->gr; 876 struct gr_gk20a *gr = &g->gr;
877 u32 tpc_mask; 877 u32 tpc_mask;
@@ -889,13 +889,13 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g)
889 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1))); 889 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1)));
890} 890}
891 891
892static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, 892int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
893 bool *post_event) 893 bool *post_event)
894{ 894{
895 return 0; 895 return 0;
896} 896}
897 897
898static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, 898int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,
899 struct zbc_query_params *query_params) 899 struct zbc_query_params *query_params)
900{ 900{
901 u32 index = query_params->index_size; 901 u32 index = query_params->index_size;
@@ -911,7 +911,7 @@ static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr,
911 return 0; 911 return 0;
912} 912}
913 913
914static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, 914bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
915 struct zbc_entry *zbc_val, int *ret_val) 915 struct zbc_entry *zbc_val, int *ret_val)
916{ 916{
917 struct zbc_s_table *s_tbl; 917 struct zbc_s_table *s_tbl;
@@ -950,7 +950,7 @@ static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr,
950 return added; 950 return added;
951} 951}
952 952
953static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, 953int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
954 struct zbc_entry *stencil_val, u32 index) 954 struct zbc_entry *stencil_val, u32 index)
955{ 955{
956 u32 zbc_s; 956 u32 zbc_s;
@@ -974,7 +974,7 @@ static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
974 return 0; 974 return 0;
975} 975}
976 976
977static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, 977int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
978 struct gr_gk20a *gr) 978 struct gr_gk20a *gr)
979{ 979{
980 struct zbc_entry zbc_val; 980 struct zbc_entry zbc_val;
@@ -1005,7 +1005,7 @@ static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g,
1005 return 0; 1005 return 0;
1006} 1006}
1007 1007
1008static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) 1008int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)
1009{ 1009{
1010 int ret; 1010 int ret;
1011 u32 i; 1011 u32 i;
@@ -1025,12 +1025,12 @@ static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr)
1025 return 0; 1025 return 0;
1026} 1026}
1027 1027
1028static u32 gr_gv11b_pagepool_default_size(struct gk20a *g) 1028u32 gr_gv11b_pagepool_default_size(struct gk20a *g)
1029{ 1029{
1030 return gr_scc_pagepool_total_pages_hwmax_value_v(); 1030 return gr_scc_pagepool_total_pages_hwmax_value_v();
1031} 1031}
1032 1032
1033static int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) 1033int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g)
1034{ 1034{
1035 struct gr_gk20a *gr = &g->gr; 1035 struct gr_gk20a *gr = &g->gr;
1036 int size; 1036 int size;
@@ -1138,7 +1138,7 @@ static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
1138 } 1138 }
1139} 1139}
1140 1140
1141static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, 1141int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
1142 u32 class_num, u32 offset, u32 data) 1142 u32 class_num, u32 offset, u32 data)
1143{ 1143{
1144 gk20a_dbg_fn(""); 1144 gk20a_dbg_fn("");
@@ -1192,7 +1192,7 @@ fail:
1192 return -EINVAL; 1192 return -EINVAL;
1193} 1193}
1194 1194
1195static void gr_gv11b_bundle_cb_defaults(struct gk20a *g) 1195void gr_gv11b_bundle_cb_defaults(struct gk20a *g)
1196{ 1196{
1197 struct gr_gk20a *gr = &g->gr; 1197 struct gr_gk20a *gr = &g->gr;
1198 1198
@@ -1204,7 +1204,7 @@ static void gr_gv11b_bundle_cb_defaults(struct gk20a *g)
1204 gr_pd_ab_dist_cfg2_token_limit_init_v(); 1204 gr_pd_ab_dist_cfg2_token_limit_init_v();
1205} 1205}
1206 1206
1207static void gr_gv11b_cb_size_default(struct gk20a *g) 1207void gr_gv11b_cb_size_default(struct gk20a *g)
1208{ 1208{
1209 struct gr_gk20a *gr = &g->gr; 1209 struct gr_gk20a *gr = &g->gr;
1210 1210
@@ -1215,7 +1215,7 @@ static void gr_gv11b_cb_size_default(struct gk20a *g)
1215 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 1215 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
1216} 1216}
1217 1217
1218static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) 1218void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
1219{ 1219{
1220 struct gr_gk20a *gr = &g->gr; 1220 struct gr_gk20a *gr = &g->gr;
1221 u32 gpc_index, ppc_index, stride, val; 1221 u32 gpc_index, ppc_index, stride, val;
@@ -1261,7 +1261,7 @@ static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
1261 } 1261 }
1262} 1262}
1263 1263
1264static void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) 1264void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data)
1265{ 1265{
1266 struct gr_gk20a *gr = &g->gr; 1266 struct gr_gk20a *gr = &g->gr;
1267 u32 gpc_index, ppc_index, stride, val; 1267 u32 gpc_index, ppc_index, stride, val;
@@ -1442,7 +1442,7 @@ static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
1442 return 0; 1442 return 0;
1443} 1443}
1444 1444
1445static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, 1445int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
1446 struct gk20a_debug_output *o) 1446 struct gk20a_debug_output *o)
1447{ 1447{
1448 struct gr_gk20a *gr = &g->gr; 1448 struct gr_gk20a *gr = &g->gr;
@@ -1595,7 +1595,7 @@ static bool gr_activity_empty_or_preempted(u32 val)
1595 return true; 1595 return true;
1596} 1596}
1597 1597
1598static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, 1598int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1599 u32 expect_delay) 1599 u32 expect_delay)
1600{ 1600{
1601 u32 delay = expect_delay; 1601 u32 delay = expect_delay;
@@ -1647,7 +1647,7 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms,
1647 return -EAGAIN; 1647 return -EAGAIN;
1648} 1648}
1649 1649
1650static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, 1650void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
1651 struct channel_ctx_gk20a *ch_ctx, 1651 struct channel_ctx_gk20a *ch_ctx,
1652 u64 addr, bool patch) 1652 u64 addr, bool patch)
1653{ 1653{
@@ -1676,7 +1676,7 @@ static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g,
1676} 1676}
1677 1677
1678 1678
1679static void gr_gv11b_init_cyclestats(struct gk20a *g) 1679void gr_gv11b_init_cyclestats(struct gk20a *g)
1680{ 1680{
1681#if defined(CONFIG_GK20A_CYCLE_STATS) 1681#if defined(CONFIG_GK20A_CYCLE_STATS)
1682 g->gpu_characteristics.flags |= 1682 g->gpu_characteristics.flags |=
@@ -1688,7 +1688,7 @@ static void gr_gv11b_init_cyclestats(struct gk20a *g)
1688#endif 1688#endif
1689} 1689}
1690 1690
1691static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 1691void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1692{ 1692{
1693#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) 1693#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
1694 tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); 1694 tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0);
@@ -1706,7 +1706,7 @@ static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1706 tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); 1706 tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
1707} 1707}
1708 1708
1709static void gr_gv11b_get_access_map(struct gk20a *g, 1709void gr_gv11b_get_access_map(struct gk20a *g,
1710 u32 **whitelist, int *num_entries) 1710 u32 **whitelist, int *num_entries)
1711{ 1711{
1712 static u32 wl_addr_gv11b[] = { 1712 static u32 wl_addr_gv11b[] = {
@@ -1751,7 +1751,7 @@ static void gr_gv11b_get_access_map(struct gk20a *g,
1751 * 1751 *
1752 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing 1752 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing
1753 */ 1753 */
1754static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, 1754int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
1755 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, 1755 u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
1756 bool sm_debugger_attached, struct channel_gk20a *fault_ch, 1756 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
1757 bool *early_exit, bool *ignore_debugger) 1757 bool *early_exit, bool *ignore_debugger)
@@ -1940,7 +1940,7 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr)
1940 } 1940 }
1941} 1941}
1942 1942
1943static int gr_gv11b_handle_fecs_error(struct gk20a *g, 1943int gr_gv11b_handle_fecs_error(struct gk20a *g,
1944 struct channel_gk20a *__ch, 1944 struct channel_gk20a *__ch,
1945 struct gr_gk20a_isr_data *isr_data) 1945 struct gr_gk20a_isr_data *isr_data)
1946{ 1946{
@@ -1957,7 +1957,7 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g,
1957 return ret; 1957 return ret;
1958} 1958}
1959 1959
1960static int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) 1960int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr)
1961{ 1961{
1962 u32 map; 1962 u32 map;
1963 u32 i, j, mapregs; 1963 u32 i, j, mapregs;
@@ -2034,7 +2034,7 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index)
2034 } 2034 }
2035} 2035}
2036 2036
2037static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) 2037int gr_gv11b_init_sw_veid_bundle(struct gk20a *g)
2038{ 2038{
2039 struct av_list_gk20a *sw_veid_bundle_init = 2039 struct av_list_gk20a *sw_veid_bundle_init =
2040 &g->gr.ctx_vars.sw_veid_bundle_init; 2040 &g->gr.ctx_vars.sw_veid_bundle_init;
@@ -2099,7 +2099,7 @@ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
2099 } 2099 }
2100} 2100}
2101 2101
2102static void gr_gv11b_detect_sm_arch(struct gk20a *g) 2102void gr_gv11b_detect_sm_arch(struct gk20a *g)
2103{ 2103{
2104 u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); 2104 u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r());
2105 2105
@@ -2111,7 +2111,7 @@ static void gr_gv11b_detect_sm_arch(struct gk20a *g)
2111 gr_gpc0_tpc0_sm_arch_warp_count_v(v); 2111 gr_gpc0_tpc0_sm_arch_warp_count_v(v);
2112} 2112}
2113 2113
2114static void gr_gv11b_init_sm_id_table(struct gk20a *g) 2114void gr_gv11b_init_sm_id_table(struct gk20a *g)
2115{ 2115{
2116 u32 gpc, tpc, sm; 2116 u32 gpc, tpc, sm;
2117 u32 sm_id = 0; 2117 u32 sm_id = 0;
@@ -2138,7 +2138,7 @@ static void gr_gv11b_init_sm_id_table(struct gk20a *g)
2138 nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); 2138 nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm);
2139} 2139}
2140 2140
2141static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, 2141void gr_gv11b_program_sm_id_numbering(struct gk20a *g,
2142 u32 gpc, u32 tpc, u32 smid) 2142 u32 gpc, u32 tpc, u32 smid)
2143{ 2143{
2144 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 2144 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -2156,7 +2156,7 @@ static void gr_gv11b_program_sm_id_numbering(struct gk20a *g,
2156 gr_gpc0_tpc0_pe_cfg_smid_value_f(global_tpc_index)); 2156 gr_gpc0_tpc0_pe_cfg_smid_value_f(global_tpc_index));
2157} 2157}
2158 2158
2159static int gr_gv11b_load_smid_config(struct gk20a *g) 2159int gr_gv11b_load_smid_config(struct gk20a *g)
2160{ 2160{
2161 u32 *tpc_sm_id; 2161 u32 *tpc_sm_id;
2162 u32 i, j; 2162 u32 i, j;
@@ -2204,7 +2204,7 @@ static int gr_gv11b_load_smid_config(struct gk20a *g)
2204 return 0; 2204 return 0;
2205} 2205}
2206 2206
2207static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) 2207int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
2208{ 2208{
2209 u32 addr_lo; 2209 u32 addr_lo;
2210 u32 addr_hi; 2210 u32 addr_hi;
@@ -2239,7 +2239,7 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
2239 2239
2240 2240
2241 2241
2242static int gr_gv11b_commit_global_timeslice(struct gk20a *g, 2242int gr_gv11b_commit_global_timeslice(struct gk20a *g,
2243 struct channel_gk20a *c, bool patch) 2243 struct channel_gk20a *c, bool patch)
2244{ 2244{
2245 struct channel_ctx_gk20a *ch_ctx = NULL; 2245 struct channel_ctx_gk20a *ch_ctx = NULL;
@@ -2292,7 +2292,7 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g,
2292 return 0; 2292 return 0;
2293} 2293}
2294 2294
2295static void gv11b_restore_context_header(struct gk20a *g, 2295void gv11b_restore_context_header(struct gk20a *g,
2296 struct nvgpu_mem *ctxheader) 2296 struct nvgpu_mem *ctxheader)
2297{ 2297{
2298 u32 va_lo, va_hi; 2298 u32 va_lo, va_hi;
@@ -2314,7 +2314,7 @@ static void gv11b_restore_context_header(struct gk20a *g,
2314 nvgpu_mem_wr(g, ctxheader, 2314 nvgpu_mem_wr(g, ctxheader,
2315 ctxsw_prog_main_image_num_save_ops_o(), 0); 2315 ctxsw_prog_main_image_num_save_ops_o(), 0);
2316} 2316}
2317static void gr_gv11b_write_zcull_ptr(struct gk20a *g, 2317void gr_gv11b_write_zcull_ptr(struct gk20a *g,
2318 struct nvgpu_mem *mem, u64 gpu_va) 2318 struct nvgpu_mem *mem, u64 gpu_va)
2319{ 2319{
2320 u32 va_lo, va_hi; 2320 u32 va_lo, va_hi;
@@ -2329,7 +2329,7 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g,
2329} 2329}
2330 2330
2331 2331
2332static void gr_gv11b_write_pm_ptr(struct gk20a *g, 2332void gr_gv11b_write_pm_ptr(struct gk20a *g,
2333 struct nvgpu_mem *mem, u64 gpu_va) 2333 struct nvgpu_mem *mem, u64 gpu_va)
2334{ 2334{
2335 u32 va_lo, va_hi; 2335 u32 va_lo, va_hi;
@@ -2343,7 +2343,7 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g,
2343 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); 2343 ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi);
2344} 2344}
2345 2345
2346static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) 2346void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
2347{ 2347{
2348 u32 gate_ctrl; 2348 u32 gate_ctrl;
2349 2349
@@ -2375,7 +2375,7 @@ static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
2375 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); 2375 gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl);
2376} 2376}
2377 2377
2378static void gr_gv11b_load_tpc_mask(struct gk20a *g) 2378void gr_gv11b_load_tpc_mask(struct gk20a *g)
2379{ 2379{
2380 u32 pes_tpc_mask = 0, fuse_tpc_mask; 2380 u32 pes_tpc_mask = 0, fuse_tpc_mask;
2381 u32 gpc, pes, val; 2381 u32 gpc, pes, val;
@@ -2405,7 +2405,7 @@ static void gr_gv11b_load_tpc_mask(struct gk20a *g)
2405 2405
2406} 2406}
2407 2407
2408static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, 2408void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
2409 struct nvgpu_mem *mem, u64 gpu_va) 2409 struct nvgpu_mem *mem, u64 gpu_va)
2410{ 2410{
2411 u32 addr_lo, addr_hi; 2411 u32 addr_lo, addr_hi;
@@ -2426,7 +2426,7 @@ static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
2426 2426
2427} 2427}
2428 2428
2429static int gr_gv11b_init_fs_state(struct gk20a *g) 2429int gr_gv11b_init_fs_state(struct gk20a *g)
2430{ 2430{
2431 u32 data; 2431 u32 data;
2432 2432
@@ -2451,7 +2451,7 @@ static int gr_gv11b_init_fs_state(struct gk20a *g)
2451 return gr_gm20b_init_fs_state(g); 2451 return gr_gm20b_init_fs_state(g);
2452} 2452}
2453 2453
2454static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, 2454void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
2455 u32 *esr_sm_sel) 2455 u32 *esr_sm_sel)
2456{ 2456{
2457 u32 reg_val; 2457 u32 reg_val;
@@ -2469,7 +2469,7 @@ static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
2469 "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); 2469 "esr_sm_sel bitmask: 0x%x", *esr_sm_sel);
2470} 2470}
2471 2471
2472static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) 2472int gv11b_gr_sm_trigger_suspend(struct gk20a *g)
2473{ 2473{
2474 u32 dbgr_control0; 2474 u32 dbgr_control0;
2475 2475
@@ -2491,7 +2491,7 @@ static int gv11b_gr_sm_trigger_suspend(struct gk20a *g)
2491 return 0; 2491 return 0;
2492} 2492}
2493 2493
2494static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) 2494void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state)
2495{ 2495{
2496 /* Check if we have at least one valid warp 2496 /* Check if we have at least one valid warp
2497 * get paused state on maxwell 2497 * get paused state on maxwell
@@ -2559,7 +2559,7 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state)
2559 } 2559 }
2560} 2560}
2561 2561
2562static int gv11b_gr_update_sm_error_state(struct gk20a *g, 2562int gv11b_gr_update_sm_error_state(struct gk20a *g,
2563 struct channel_gk20a *ch, u32 sm_id, 2563 struct channel_gk20a *ch, u32 sm_id,
2564 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) 2564 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state)
2565{ 2565{
@@ -2638,7 +2638,7 @@ fail:
2638 return err; 2638 return err;
2639} 2639}
2640 2640
2641static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, 2641int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
2642 struct channel_gk20a *ch, u64 sms, bool enable) 2642 struct channel_gk20a *ch, u64 sms, bool enable)
2643{ 2643{
2644 struct nvgpu_dbg_gpu_reg_op *ops; 2644 struct nvgpu_dbg_gpu_reg_op *ops;
@@ -2697,7 +2697,7 @@ static int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
2697 return err; 2697 return err;
2698} 2698}
2699 2699
2700static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) 2700int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
2701{ 2701{
2702 int sm_id; 2702 int sm_id;
2703 struct gr_gk20a *gr = &g->gr; 2703 struct gr_gk20a *gr = &g->gr;
@@ -2737,7 +2737,7 @@ static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
2737 return 0; 2737 return 0;
2738} 2738}
2739 2739
2740static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) 2740void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g)
2741{ 2741{
2742 2742
2743 /* clear hww */ 2743 /* clear hww */
@@ -2767,7 +2767,7 @@ static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g)
2767 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); 2767 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f());
2768} 2768}
2769 2769
2770static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) 2770bool gv11b_gr_sm_debugger_attached(struct gk20a *g)
2771{ 2771{
2772 u32 debugger_mode; 2772 u32 debugger_mode;
2773 u32 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); 2773 u32 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r());
@@ -2787,7 +2787,7 @@ static bool gv11b_gr_sm_debugger_attached(struct gk20a *g)
2787 return false; 2787 return false;
2788} 2788}
2789 2789
2790static void gv11b_gr_suspend_single_sm(struct gk20a *g, 2790void gv11b_gr_suspend_single_sm(struct gk20a *g,
2791 u32 gpc, u32 tpc, u32 sm, 2791 u32 gpc, u32 tpc, u32 sm,
2792 u32 global_esr_mask, bool check_errors) 2792 u32 global_esr_mask, bool check_errors)
2793{ 2793{
@@ -2823,7 +2823,7 @@ static void gv11b_gr_suspend_single_sm(struct gk20a *g,
2823 } 2823 }
2824} 2824}
2825 2825
2826static void gv11b_gr_suspend_all_sms(struct gk20a *g, 2826void gv11b_gr_suspend_all_sms(struct gk20a *g,
2827 u32 global_esr_mask, bool check_errors) 2827 u32 global_esr_mask, bool check_errors)
2828{ 2828{
2829 struct gr_gk20a *gr = &g->gr; 2829 struct gr_gk20a *gr = &g->gr;
@@ -2868,7 +2868,7 @@ static void gv11b_gr_suspend_all_sms(struct gk20a *g,
2868 } 2868 }
2869} 2869}
2870 2870
2871static void gv11b_gr_resume_single_sm(struct gk20a *g, 2871void gv11b_gr_resume_single_sm(struct gk20a *g,
2872 u32 gpc, u32 tpc, u32 sm) 2872 u32 gpc, u32 tpc, u32 sm)
2873{ 2873{
2874 u32 dbgr_control0, dbgr_status0; 2874 u32 dbgr_control0, dbgr_status0;
@@ -2936,7 +2936,7 @@ static void gv11b_gr_resume_single_sm(struct gk20a *g,
2936 2936
2937} 2937}
2938 2938
2939static void gv11b_gr_resume_all_sms(struct gk20a *g) 2939void gv11b_gr_resume_all_sms(struct gk20a *g)
2940{ 2940{
2941 u32 dbgr_control0, dbgr_status0; 2941 u32 dbgr_control0, dbgr_status0;
2942 /* 2942 /*
@@ -3001,7 +3001,7 @@ static void gv11b_gr_resume_all_sms(struct gk20a *g)
3001 dbgr_control0, dbgr_status0); 3001 dbgr_control0, dbgr_status0);
3002} 3002}
3003 3003
3004static int gv11b_gr_resume_from_pause(struct gk20a *g) 3004int gv11b_gr_resume_from_pause(struct gk20a *g)
3005{ 3005{
3006 int err = 0; 3006 int err = 0;
3007 u32 reg_val; 3007 u32 reg_val;
@@ -3020,7 +3020,7 @@ static int gv11b_gr_resume_from_pause(struct gk20a *g)
3020 return err; 3020 return err;
3021} 3021}
3022 3022
3023static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, 3023u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g,
3024 u32 gpc, u32 tpc, u32 sm) 3024 u32 gpc, u32 tpc, u32 sm)
3025{ 3025{
3026 u32 offset = gk20a_gr_gpc_offset(g, gpc) + 3026 u32 offset = gk20a_gr_gpc_offset(g, gpc) +
@@ -3032,7 +3032,7 @@ static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g,
3032 return hww_warp_esr; 3032 return hww_warp_esr;
3033} 3033}
3034 3034
3035static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, 3035u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g,
3036 u32 gpc, u32 tpc, u32 sm) 3036 u32 gpc, u32 tpc, u32 sm)
3037{ 3037{
3038 u32 offset = gk20a_gr_gpc_offset(g, gpc) + 3038 u32 offset = gk20a_gr_gpc_offset(g, gpc) +
@@ -3045,7 +3045,7 @@ static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g,
3045 return hww_global_esr; 3045 return hww_global_esr;
3046} 3046}
3047 3047
3048static u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) 3048u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g)
3049{ 3049{
3050 /* 3050 /*
3051 * These three interrupts don't require locking down the SM. They can 3051 * These three interrupts don't require locking down the SM. They can
@@ -3104,7 +3104,7 @@ static void gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(struct gk20a *g,
3104 warps_paused, warps_trapped); 3104 warps_paused, warps_trapped);
3105} 3105}
3106 3106
3107static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, 3107int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g,
3108 u32 gpc, u32 tpc, u32 sm, 3108 u32 gpc, u32 tpc, u32 sm,
3109 u32 global_esr_mask, bool check_errors) 3109 u32 global_esr_mask, bool check_errors)
3110{ 3110{
@@ -3190,7 +3190,7 @@ static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g,
3190 return -ETIMEDOUT; 3190 return -ETIMEDOUT;
3191} 3191}
3192 3192
3193static int gv11b_gr_lock_down_sm(struct gk20a *g, 3193int gv11b_gr_lock_down_sm(struct gk20a *g,
3194 u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, 3194 u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask,
3195 bool check_errors) 3195 bool check_errors)
3196{ 3196{
@@ -3212,7 +3212,7 @@ static int gv11b_gr_lock_down_sm(struct gk20a *g,
3212 check_errors); 3212 check_errors);
3213} 3213}
3214 3214
3215static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, 3215void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
3216 u32 global_esr) 3216 u32 global_esr)
3217{ 3217{
3218 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + 3218 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) +
@@ -3232,7 +3232,7 @@ static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
3232 offset)); 3232 offset));
3233} 3233}
3234 3234
3235static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, 3235int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
3236 u32 gpc, u32 tpc, bool *post_event) 3236 u32 gpc, u32 tpc, bool *post_event)
3237{ 3237{
3238 u32 esr; 3238 u32 esr;
@@ -3263,7 +3263,7 @@ static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
3263static const u32 _num_ovr_perf_regs = 20; 3263static const u32 _num_ovr_perf_regs = 20;
3264static u32 _ovr_perf_regs[20] = { 0, }; 3264static u32 _ovr_perf_regs[20] = { 0, };
3265 3265
3266static void gv11b_gr_init_ovr_sm_dsm_perf(void) 3266void gv11b_gr_init_ovr_sm_dsm_perf(void)
3267{ 3267{
3268 if (_ovr_perf_regs[0] != 0) 3268 if (_ovr_perf_regs[0] != 0)
3269 return; 3269 return;
@@ -3301,7 +3301,7 @@ static const u32 _num_sm_dsm_perf_ctrl_regs = 2;
3301static u32 *_sm_dsm_perf_regs; 3301static u32 *_sm_dsm_perf_regs;
3302static u32 _sm_dsm_perf_ctrl_regs[2]; 3302static u32 _sm_dsm_perf_ctrl_regs[2];
3303 3303
3304static void gv11b_gr_init_sm_dsm_reg_info(void) 3304void gv11b_gr_init_sm_dsm_reg_info(void)
3305{ 3305{
3306 if (_sm_dsm_perf_ctrl_regs[0] != 0) 3306 if (_sm_dsm_perf_ctrl_regs[0] != 0)
3307 return; 3307 return;
@@ -3312,7 +3312,7 @@ static void gv11b_gr_init_sm_dsm_reg_info(void)
3312 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(); 3312 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r();
3313} 3313}
3314 3314
3315static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, 3315void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g,
3316 u32 *num_sm_dsm_perf_regs, 3316 u32 *num_sm_dsm_perf_regs,
3317 u32 **sm_dsm_perf_regs, 3317 u32 **sm_dsm_perf_regs,
3318 u32 *perf_register_stride) 3318 u32 *perf_register_stride)
@@ -3323,7 +3323,7 @@ static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g,
3323 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); 3323 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v();
3324} 3324}
3325 3325
3326static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, 3326void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
3327 u32 *num_sm_dsm_perf_ctrl_regs, 3327 u32 *num_sm_dsm_perf_ctrl_regs,
3328 u32 **sm_dsm_perf_ctrl_regs, 3328 u32 **sm_dsm_perf_ctrl_regs,
3329 u32 *ctrl_register_stride) 3329 u32 *ctrl_register_stride)
@@ -3334,14 +3334,14 @@ static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
3334 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); 3334 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v();
3335} 3335}
3336 3336
3337static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, 3337void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
3338 u32 **ovr_perf_regs) 3338 u32 **ovr_perf_regs)
3339{ 3339{
3340 *num_ovr_perf_regs = _num_ovr_perf_regs; 3340 *num_ovr_perf_regs = _num_ovr_perf_regs;
3341 *ovr_perf_regs = _ovr_perf_regs; 3341 *ovr_perf_regs = _ovr_perf_regs;
3342} 3342}
3343 3343
3344static void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) 3344void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset)
3345{ 3345{
3346 u32 reg_val; 3346 u32 reg_val;
3347 u32 quad_ctrl; 3347 u32 quad_ctrl;
@@ -3393,7 +3393,7 @@ static bool pri_is_egpc_addr_shared(struct gk20a *g, u32 addr)
3393 (addr < egpc_shared_base + gpc_stride); 3393 (addr < egpc_shared_base + gpc_stride);
3394} 3394}
3395 3395
3396static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) 3396bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr)
3397{ 3397{
3398 u32 egpc_base = g->ops.gr.get_egpc_base(g); 3398 u32 egpc_base = g->ops.gr.get_egpc_base(g);
3399 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 3399 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -3404,7 +3404,7 @@ static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr)
3404 pri_is_egpc_addr_shared(g, addr); 3404 pri_is_egpc_addr_shared(g, addr);
3405} 3405}
3406 3406
3407static bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) 3407bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr)
3408{ 3408{
3409 u32 egpc_addr = 0; 3409 u32 egpc_addr = 0;
3410 3410
@@ -3454,7 +3454,7 @@ static u32 pri_etpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc)
3454 addr; 3454 addr;
3455} 3455}
3456 3456
3457static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, 3457void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr,
3458 u32 *egpc_num, u32 *etpc_num) 3458 u32 *egpc_num, u32 *etpc_num)
3459{ 3459{
3460 u32 egpc_addr = 0; 3460 u32 egpc_addr = 0;
@@ -3467,7 +3467,7 @@ static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr,
3467 "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); 3467 "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num);
3468} 3468}
3469 3469
3470static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, 3470int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type,
3471 u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) 3471 u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags)
3472{ 3472{
3473 u32 gpc_addr; 3473 u32 gpc_addr;
@@ -3506,7 +3506,7 @@ static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type,
3506 return -EINVAL; 3506 return -EINVAL;
3507} 3507}
3508 3508
3509static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, 3509void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
3510 u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t) 3510 u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t)
3511{ 3511{
3512 u32 gpc_num, tpc_num; 3512 u32 gpc_num, tpc_num;
@@ -3569,12 +3569,12 @@ static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
3569 } 3569 }
3570} 3570}
3571 3571
3572static u32 gv11b_gr_get_egpc_base(struct gk20a *g) 3572u32 gv11b_gr_get_egpc_base(struct gk20a *g)
3573{ 3573{
3574 return EGPC_PRI_BASE; 3574 return EGPC_PRI_BASE;
3575} 3575}
3576 3576
3577static void gr_gv11b_init_gpc_mmu(struct gk20a *g) 3577void gr_gv11b_init_gpc_mmu(struct gk20a *g)
3578{ 3578{
3579 u32 temp; 3579 u32 temp;
3580 3580
@@ -3606,104 +3606,3 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g)
3606 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), 3606 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
3607 gk20a_readl(g, fb_mmu_debug_rd_r())); 3607 gk20a_readl(g, fb_mmu_debug_rd_r()));
3608} 3608}
3609
3610void gv11b_init_gr(struct gk20a *g)
3611{
3612 struct gpu_ops *gops = &g->ops;
3613
3614 gp10b_init_gr(g);
3615 gops->gr.init_preemption_state = NULL;
3616 gops->gr.init_fs_state = gr_gv11b_init_fs_state;
3617 gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch;
3618 gops->gr.is_valid_class = gr_gv11b_is_valid_class;
3619 gops->gr.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class;
3620 gops->gr.is_valid_compute_class = gr_gv11b_is_valid_compute_class;
3621 gops->gr.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va;
3622 gops->gr.add_zbc_s = gr_gv11b_add_zbc_stencil;
3623 gops->gr.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl;
3624 gops->gr.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl;
3625 gops->gr.zbc_s_query_table = gr_gv11b_zbc_s_query_table;
3626 gops->gr.add_zbc_type_s = gr_gv11b_add_zbc_type_s;
3627 gops->gr.pagepool_default_size = gr_gv11b_pagepool_default_size;
3628 gops->gr.calc_global_ctx_buffer_size =
3629 gr_gv11b_calc_global_ctx_buffer_size;
3630 gops->gr.commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb;
3631 gops->gr.handle_sw_method = gr_gv11b_handle_sw_method;
3632 gops->gr.bundle_cb_defaults = gr_gv11b_bundle_cb_defaults;
3633 gops->gr.cb_size_default = gr_gv11b_cb_size_default;
3634 gops->gr.set_alpha_circular_buffer_size =
3635 gr_gv11b_set_alpha_circular_buffer_size;
3636 gops->gr.set_circular_buffer_size =
3637 gr_gv11b_set_circular_buffer_size;
3638 gops->gr.dump_gr_regs = gr_gv11b_dump_gr_status_regs;
3639 gops->gr.wait_empty = gr_gv11b_wait_empty;
3640 gops->gr.init_cyclestats = gr_gv11b_init_cyclestats;
3641 gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask;
3642 gops->gr.get_access_map = gr_gv11b_get_access_map;
3643 gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception;
3644 gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception;
3645 gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception;
3646 gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions;
3647 gops->gr.enable_exceptions = gr_gv11b_enable_exceptions;
3648 gops->gr.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions;
3649 gops->gr.pre_process_sm_exception =
3650 gr_gv11b_pre_process_sm_exception;
3651 gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error;
3652 gops->gr.create_gr_sysfs = gr_gv11b_create_sysfs;
3653 gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping;
3654 gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle;
3655 gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping;
3656 gops->gr.commit_global_timeslice = gr_gv11b_commit_global_timeslice;
3657 gops->gr.init_sm_id_table = gr_gv11b_init_sm_id_table;
3658 gops->gr.load_smid_config = gr_gv11b_load_smid_config;
3659 gops->gr.program_sm_id_numbering =
3660 gr_gv11b_program_sm_id_numbering;
3661 gops->gr.commit_inst = gr_gv11b_commit_inst;
3662 gops->gr.restore_context_header = gv11b_restore_context_header;
3663 gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr;
3664 gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr;
3665 gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode;
3666 gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask;
3667 gops->gr.handle_gpc_gpccs_exception =
3668 gr_gv11b_handle_gpc_gpccs_exception;
3669 gops->gr.set_czf_bypass = NULL;
3670 gops->gr.handle_gpc_gpcmmu_exception =
3671 gr_gv11b_handle_gpc_gpcmmu_exception;
3672 gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel;
3673 gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend;
3674 gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info;
3675 gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state;
3676 gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode;
3677 gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state;
3678 gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask;
3679 gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached;
3680 gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm;
3681 gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms;
3682 gops->gr.resume_single_sm = gv11b_gr_resume_single_sm;
3683 gops->gr.resume_all_sms = gv11b_gr_resume_all_sms;
3684 gops->gr.resume_from_pause = gv11b_gr_resume_from_pause;
3685 gops->gr.get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr;
3686 gops->gr.get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr;
3687 gops->gr.get_sm_no_lock_down_hww_global_esr_mask =
3688 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask;
3689 gops->gr.lock_down_sm = gv11b_gr_lock_down_sm;
3690 gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down;
3691 gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww;
3692 gops->gr.handle_tpc_sm_ecc_exception =
3693 gr_gv11b_handle_tpc_sm_ecc_exception;
3694 gops->gr.handle_tpc_mpc_exception =
3695 gr_gv11b_handle_tpc_mpc_exception;
3696 gops->gr.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf;
3697 gops->gr.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info;
3698 gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs;
3699 gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs;
3700 gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs;
3701 gops->gr.access_smpc_reg = gv11b_gr_access_smpc_reg;
3702 gops->gr.decode_egpc_addr = gv11b_gr_decode_egpc_addr;
3703 gops->gr.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table;
3704 gops->gr.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num;
3705 gops->gr.get_egpc_base = gv11b_gr_get_egpc_base;
3706 gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr;
3707 gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr;
3708 gops->gr.init_gpc_mmu = gr_gv11b_init_gpc_mmu;
3709}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:10:23 -0400