diff options
author | Anup Mahindre <amahindre@nvidia.com> | 2018-09-05 00:32:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-19 18:53:56 -0400 |
commit | 7e591dced99f328f4960702dbb6235fe7dc7f6b5 (patch) | |
tree | 083e4c74b511c1fa6f785221c02e8cf8efe6ea52 /drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |
parent | a77bce7193dbd877d00a8bd69e2964db42419a8d (diff) |
gpu: nvgpu: Remove NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE API
Remove the API as it has no use cases.
Bug 200445906
Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1817629
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 90 |
1 files changed, 0 insertions, 90 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 78cb1b98..3dedc6b5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -3228,96 +3228,6 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) | |||
3228 | } | 3228 | } |
3229 | } | 3229 | } |
3230 | 3230 | ||
3231 | static void gv11b_gr_write_sm_error_state(struct gk20a *g, | ||
3232 | u32 offset, | ||
3233 | struct nvgpu_tsg_sm_error_state *sm_error_states) | ||
3234 | { | ||
3235 | nvgpu_writel(g, | ||
3236 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | ||
3237 | sm_error_states->hww_global_esr); | ||
3238 | nvgpu_writel(g, | ||
3239 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, | ||
3240 | sm_error_states->hww_warp_esr); | ||
3241 | nvgpu_writel(g, | ||
3242 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset, | ||
3243 | u64_lo32(sm_error_states->hww_warp_esr_pc)); | ||
3244 | nvgpu_writel(g, | ||
3245 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() + offset, | ||
3246 | u64_hi32(sm_error_states->hww_warp_esr_pc)); | ||
3247 | nvgpu_writel(g, | ||
3248 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset, | ||
3249 | sm_error_states->hww_global_esr_report_mask); | ||
3250 | nvgpu_writel(g, | ||
3251 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, | ||
3252 | sm_error_states->hww_warp_esr_report_mask); | ||
3253 | } | ||
3254 | |||
3255 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | ||
3256 | struct channel_gk20a *ch, u32 sm_id, | ||
3257 | struct nvgpu_tsg_sm_error_state *sm_error_state) | ||
3258 | { | ||
3259 | struct tsg_gk20a *tsg; | ||
3260 | u32 gpc, tpc, sm, offset; | ||
3261 | struct nvgpu_gr_ctx *ch_ctx; | ||
3262 | int err = 0; | ||
3263 | struct nvgpu_tsg_sm_error_state *tsg_sm_error_states; | ||
3264 | |||
3265 | tsg = tsg_gk20a_from_ch(ch); | ||
3266 | if (tsg == NULL) { | ||
3267 | return -EINVAL; | ||
3268 | } | ||
3269 | |||
3270 | ch_ctx = &tsg->gr_ctx; | ||
3271 | |||
3272 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
3273 | |||
3274 | tsg_sm_error_states = tsg->sm_error_states + sm_id; | ||
3275 | gk20a_tsg_update_sm_error_state_locked(tsg, sm_id, sm_error_state); | ||
3276 | |||
3277 | err = gr_gk20a_disable_ctxsw(g); | ||
3278 | if (err) { | ||
3279 | nvgpu_err(g, "unable to stop gr ctxsw"); | ||
3280 | goto fail; | ||
3281 | } | ||
3282 | |||
3283 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | ||
3284 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | ||
3285 | sm = g->gr.sm_to_cluster[sm_id].sm_index; | ||
3286 | |||
3287 | offset = gk20a_gr_gpc_offset(g, gpc) + | ||
3288 | gk20a_gr_tpc_offset(g, tpc) + | ||
3289 | gv11b_gr_sm_offset(g, sm); | ||
3290 | |||
3291 | if (gk20a_is_channel_ctx_resident(ch)) { | ||
3292 | gv11b_gr_write_sm_error_state(g, offset, tsg_sm_error_states); | ||
3293 | } else { | ||
3294 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | ||
3295 | if (err) { | ||
3296 | goto enable_ctxsw; | ||
3297 | } | ||
3298 | |||
3299 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
3300 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + | ||
3301 | offset, | ||
3302 | tsg_sm_error_states->hww_global_esr_report_mask, | ||
3303 | true); | ||
3304 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
3305 | gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() + | ||
3306 | offset, | ||
3307 | tsg_sm_error_states->hww_warp_esr_report_mask, | ||
3308 | true); | ||
3309 | |||
3310 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); | ||
3311 | } | ||
3312 | |||
3313 | enable_ctxsw: | ||
3314 | err = gr_gk20a_enable_ctxsw(g); | ||
3315 | |||
3316 | fail: | ||
3317 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
3318 | return err; | ||
3319 | } | ||
3320 | |||
3321 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 3231 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
3322 | struct channel_gk20a *ch, u64 sms, bool enable) | 3232 | struct channel_gk20a *ch, u64 sms, bool enable) |
3323 | { | 3233 | { |