gpu: nvgpu: gv11b: enable more gr exceptions

-pd, scc, ds, ssync, mme and sked exceptions are
 enabled. This will be useful for debugging
-Handle enabled interrupts
-Add gr ops to handle ssync hww. For legacy
 chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr.
 Since ssync hww is not enabled on legacy chips, added
 ssync hww exception handling for volta only.

Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1644751
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 38 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 6b43fcc8..3e207811 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -313,12 +313,32 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc,
 void gr_gv11b_enable_hww_exceptions(struct gk20a *g)
 {
         /* enable exceptions */
+
         gk20a_writel(g, gr_fe_hww_esr_r(),
                      gr_fe_hww_esr_en_enable_f() |
                      gr_fe_hww_esr_reset_active_f());
         gk20a_writel(g, gr_memfmt_hww_esr_r(),
                      gr_memfmt_hww_esr_en_enable_f() |
                      gr_memfmt_hww_esr_reset_active_f());
+        gk20a_writel(g, gr_pd_hww_esr_r(),
+                     gr_pd_hww_esr_en_enable_f() |
+                     gr_pd_hww_esr_reset_active_f());
+        gk20a_writel(g, gr_scc_hww_esr_r(),
+                     gr_scc_hww_esr_en_enable_f() |
+                     gr_scc_hww_esr_reset_active_f());
+        gk20a_writel(g, gr_ds_hww_esr_r(),
+                     gr_ds_hww_esr_en_enabled_f() |
+                     gr_ds_hww_esr_reset_task_f());
+        gk20a_writel(g, gr_ssync_hww_esr_r(),
+                     gr_ssync_hww_esr_en_enable_f() |
+                     gr_ssync_hww_esr_reset_active_f());
+        gk20a_writel(g, gr_mme_hww_esr_r(),
+                     gr_mme_hww_esr_en_enable_f() |
+                     gr_mme_hww_esr_reset_active_f());
+
+        /* For now leave POR values */
+        nvgpu_log(g, gpu_dbg_info, "gr_sked_hww_esr_en_r 0x%08x",
+                        gk20a_readl(g, gr_sked_hww_esr_en_r()));
 }
 
 void gr_gv11b_fecs_host_int_enable(struct gk20a *g)
@@ -351,8 +371,16 @@ void gr_gv11b_enable_exceptions(struct gk20a *g)
 
         reg_val = gr_exception_en_fe_enabled_f() |
                         gr_exception_en_memfmt_enabled_f() |
+                        gr_exception_en_pd_enabled_f() |
+                        gr_exception_en_scc_enabled_f() |
                         gr_exception_en_ds_enabled_f() |
+                        gr_exception_en_ssync_enabled_f() |
+                        gr_exception_en_mme_enabled_f() |
+                        gr_exception_en_sked_enabled_f() |
                         gr_exception_en_gpc_enabled_f();
+
+        nvgpu_log(g, gpu_dbg_info, "gr_exception_en 0x%08x", reg_val);
+
         gk20a_writel(g, gr_exception_en_r(), reg_val);
 
 }
@@ -4246,3 +4274,13 @@ u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g)
 {
         return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r();
 }
+
+int gr_gv11b_handle_ssync_hww(struct gk20a *g)
+{
+        u32 ssync = gk20a_readl(g, gr_ssync_hww_esr_r());
+
+        nvgpu_err(g, "ssync exception: esr 0x%08x", ssync);
+        gk20a_writel(g, gr_ssync_hww_esr_r(),
+                         gr_ssync_hww_esr_reset_active_f());
+        return -EFAULT;
+}