diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-05-03 16:55:27 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-30 11:43:35 -0400 |
commit | 77199c0225457c48acb2dca89d0bf93d05b33231 (patch) | |
tree | 8a14f1f8c5f0a1ac2707c4725ec52995493838cc /drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |
parent | 0181a4e60248c2e3fbb46aa3a33c6154df8b5c5f (diff) |
gpu: nvgpu: gv11b: init enable_exceptions gr ops
Enable FE, MEMFMT, DS and GPC exceptions only.
Make sure corresponding HWW_ESR are enabled too.
JIRA GPUT19X-75
Change-Id: Icf47b7e531dd72b59cbc6ac54b5902187f703d61
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1474859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8b4471ca..a9f1183e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -284,6 +284,29 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
284 | 284 | ||
285 | } | 285 | } |
286 | 286 | ||
287 | static void gr_gv11b_enable_exceptions(struct gk20a *g) | ||
288 | { | ||
289 | struct gr_gk20a *gr = &g->gr; | ||
290 | u32 reg_val; | ||
291 | |||
292 | /* | ||
293 | * clear exceptions : | ||
294 | * other than SM : hww_esr are reset in *enable_hww_excetpions* | ||
295 | * SM : cleared in *set_hww_esr_report_mask* | ||
296 | */ | ||
297 | |||
298 | /* enable exceptions */ | ||
299 | gk20a_writel(g, gr_exception2_en_r(), 0x0); /* BE not enabled */ | ||
300 | gk20a_writel(g, gr_exception1_en_r(), (1 << gr->gpc_count) - 1); | ||
301 | |||
302 | reg_val = gr_exception_en_fe_enabled_f() | | ||
303 | gr_exception_en_memfmt_enabled_f() | | ||
304 | gr_exception_en_ds_enabled_f() | | ||
305 | gr_exception_en_gpc_enabled_f(); | ||
306 | gk20a_writel(g, gr_exception_en_r(), reg_val); | ||
307 | |||
308 | } | ||
309 | |||
287 | static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | 310 | static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, |
288 | bool *post_event, struct channel_gk20a *fault_ch, | 311 | bool *post_event, struct channel_gk20a *fault_ch, |
289 | u32 *hww_global_esr) | 312 | u32 *hww_global_esr) |
@@ -2375,6 +2398,7 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2375 | gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; | 2398 | gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; |
2376 | gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; | 2399 | gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; |
2377 | gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; | 2400 | gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; |
2401 | gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; | ||
2378 | gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; | 2402 | gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; |
2379 | gops->gr.pre_process_sm_exception = | 2403 | gops->gr.pre_process_sm_exception = |
2380 | gr_gv11b_pre_process_sm_exception; | 2404 | gr_gv11b_pre_process_sm_exception; |