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authorseshendra Gadagottu <sgadagottu@nvidia.com>2016-09-07 13:22:28 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-10-12 20:07:38 -0400
commit6f29d0d8cd81f3b964fff975b917569b865b26d3 (patch)
treee30daf76afa83a87b7243ddf56fdf29ef200ed82 /drivers/gpu/nvgpu/gv11b/gr_gv11b.c
parent1a36091fb9e31578c2e01c60cbe0a9b01b64bc9e (diff)
gpu: nvgpu: gv11b: setup rop mappings
JIRA GV11B-21 Change-Id: I7695936bdac4502ceb0bdad4fc029e249eb2f05d Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1224783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c61
1 files changed, 60 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 02044df6..3488a03a 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -22,13 +22,13 @@
22#include "gk20a/dbg_gpu_gk20a.h" 22#include "gk20a/dbg_gpu_gk20a.h"
23 23
24#include "gm20b/gr_gm20b.h" 24#include "gm20b/gr_gm20b.h"
25#include "gp10b/gr_gp10b.h"
26#include "gv11b/gr_gv11b.h" 25#include "gv11b/gr_gv11b.h"
27#include "hw_gr_gv11b.h" 26#include "hw_gr_gv11b.h"
28#include "hw_fifo_gv11b.h" 27#include "hw_fifo_gv11b.h"
29#include "hw_proj_gv11b.h" 28#include "hw_proj_gv11b.h"
30#include "hw_ctxsw_prog_gv11b.h" 29#include "hw_ctxsw_prog_gv11b.h"
31#include "hw_mc_gv11b.h" 30#include "hw_mc_gv11b.h"
31#include "hw_gr_gv11b.h"
32#include <linux/vmalloc.h> 32#include <linux/vmalloc.h>
33 33
34static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) 34static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num)
@@ -1507,6 +1507,64 @@ static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr)
1507 return hww_warp_esr; 1507 return hww_warp_esr;
1508} 1508}
1509 1509
1510int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr)
1511{
1512 u32 map;
1513 u32 i, j, mapregs;
1514 u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS);
1515 u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
1516 GPU_LIT_NUM_TPC_PER_GPC);
1517
1518 gk20a_dbg_fn("");
1519
1520 if (!gr->map_tiles)
1521 return -1;
1522
1523 gk20a_writel(g, gr_crstr_map_table_cfg_r(),
1524 gr_crstr_map_table_cfg_row_offset_f(gr->map_row_offset) |
1525 gr_crstr_map_table_cfg_num_entries_f(gr->tpc_count));
1526
1527 /* 6 tpc can be stored in one map register */
1528 mapregs = (num_gpcs * num_tpc_per_gpc + 5) / 6;
1529
1530 for (i = 0, j = 0; i < mapregs; i++, j = j + 6) {
1531 map = gr_crstr_gpc_map_tile0_f(gr->map_tiles[j]) |
1532 gr_crstr_gpc_map_tile1_f(gr->map_tiles[j + 1]) |
1533 gr_crstr_gpc_map_tile2_f(gr->map_tiles[j + 2]) |
1534 gr_crstr_gpc_map_tile3_f(gr->map_tiles[j + 3]) |
1535 gr_crstr_gpc_map_tile4_f(gr->map_tiles[j + 4]) |
1536 gr_crstr_gpc_map_tile5_f(gr->map_tiles[j + 5]);
1537
1538 gk20a_writel(g, gr_crstr_gpc_map_r(i), map);
1539 gk20a_writel(g, gr_ppcs_wwdx_map_gpc_map_r(i), map);
1540 gk20a_writel(g, gr_rstr2d_gpc_map_r(i), map);
1541 }
1542
1543 gk20a_writel(g, gr_ppcs_wwdx_map_table_cfg_r(),
1544 gr_ppcs_wwdx_map_table_cfg_row_offset_f(gr->map_row_offset) |
1545 gr_ppcs_wwdx_map_table_cfg_num_entries_f(gr->tpc_count));
1546
1547 for (i = 0, j = 1; i < gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v();
1548 i++, j = j + 4) {
1549 gk20a_writel(g, gr_ppcs_wwdx_map_table_cfg_coeff_r(i),
1550 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(
1551 ((1 << j) % gr->tpc_count)) |
1552 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(
1553 ((1 << (j + 1)) % gr->tpc_count)) |
1554 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(
1555 ((1 << (j + 2)) % gr->tpc_count)) |
1556 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(
1557 ((1 << (j + 3)) % gr->tpc_count)));
1558 }
1559
1560 gk20a_writel(g, gr_rstr2d_map_table_cfg_r(),
1561 gr_rstr2d_map_table_cfg_row_offset_f(gr->map_row_offset) |
1562 gr_rstr2d_map_table_cfg_num_entries_f(gr->tpc_count));
1563
1564 return 0;
1565}
1566
1567
1510void gv11b_init_gr(struct gpu_ops *gops) 1568void gv11b_init_gr(struct gpu_ops *gops)
1511{ 1569{
1512 gp10b_init_gr(gops); 1570 gp10b_init_gr(gops);
@@ -1543,4 +1601,5 @@ void gv11b_init_gr(struct gpu_ops *gops)
1543 gops->gr.pre_process_sm_exception = 1601 gops->gr.pre_process_sm_exception =
1544 gr_gv11b_pre_process_sm_exception; 1602 gr_gv11b_pre_process_sm_exception;
1545 gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; 1603 gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error;
1604 gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping;
1546} 1605}