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authorSrirangan <smadhavan@nvidia.com>2018-08-02 05:47:55 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-10 01:28:15 -0400
commit6b26d233499f9d447f06e8e72c72ed6728762e37 (patch)
treed983b078e372165b44e51d119e9b4b61ac9bbc1c /drivers/gpu/nvgpu/gv11b/gr_gv11b.c
parent9c13b30a465ed94f1e3547dc439462c3ea496eb8 (diff)
gpu: nvgpu: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces including single statement loop bodies. This patch fix the MISRA violations due to single statement loop bodies without braces by adding them. JIRA NVGPU-989 Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791194 Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 9e36071f..791c0d6f 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2801,8 +2801,9 @@ int gr_gv11b_load_smid_config(struct gk20a *g)
2801 gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg); 2801 gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg);
2802 } 2802 }
2803 2803
2804 for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) 2804 for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) {
2805 gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]); 2805 gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]);
2806 }
2806 nvgpu_kfree(g, tpc_sm_id); 2807 nvgpu_kfree(g, tpc_sm_id);
2807 2808
2808 return 0; 2809 return 0;
@@ -4894,11 +4895,12 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
4894 if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) 4895 if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC)
4895 for (tpc_num = 0; 4896 for (tpc_num = 0;
4896 tpc_num < g->gr.gpc_tpc_count[gpc_num]; 4897 tpc_num < g->gr.gpc_tpc_count[gpc_num];
4897 tpc_num++) 4898 tpc_num++) {
4898 priv_addr_table[t++] = 4899 priv_addr_table[t++] =
4899 pri_tpc_addr(g, 4900 pri_tpc_addr(g,
4900 pri_tpccs_addr_mask(addr), 4901 pri_tpccs_addr_mask(addr),
4901 gpc_num, tpc_num); 4902 gpc_num, tpc_num);
4903 }
4902 4904
4903 else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) { 4905 else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) {
4904 err = gr_gk20a_split_ppc_broadcast_addr(g, 4906 err = gr_gk20a_split_ppc_broadcast_addr(g,
@@ -4998,11 +5000,12 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
4998 if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) 5000 if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC)
4999 for (tpc_num = 0; 5001 for (tpc_num = 0;
5000 tpc_num < g->gr.gpc_tpc_count[gpc_num]; 5002 tpc_num < g->gr.gpc_tpc_count[gpc_num];
5001 tpc_num++) 5003 tpc_num++) {
5002 priv_addr_table[t++] = 5004 priv_addr_table[t++] =
5003 pri_tpc_addr(g, 5005 pri_tpc_addr(g,
5004 pri_tpccs_addr_mask(addr), 5006 pri_tpccs_addr_mask(addr),
5005 gpc_num, tpc_num); 5007 gpc_num, tpc_num);
5008 }
5006 else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) 5009 else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC)
5007 err = gr_gk20a_split_ppc_broadcast_addr(g, 5010 err = gr_gk20a_split_ppc_broadcast_addr(g,
5008 addr, gpc_num, priv_addr_table, &t); 5011 addr, gpc_num, priv_addr_table, &t);