gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG

Added sw method for NVC397_SET_TEX_IN_DBG with
following data fields:
data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE
data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD
data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST

Bug 1934197

Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1507479
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 542ed1ff..7993e071 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1069,6 +1069,31 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
         gk20a_dbg_fn("done");
 }
 
+static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data)
+{
+        u32 val;
+        bool flag;
+
+        gk20a_dbg_fn("");
+
+        val = gk20a_readl(g, gr_gpcs_tpcs_tex_in_dbg_r());
+        flag = (data & NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE) ? 1 : 0;
+        val = set_field(val, gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(),
+                        gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(flag));
+        gk20a_writel(g, gr_gpcs_tpcs_tex_in_dbg_r(), val);
+
+        val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r());
+        flag = (data &
+                NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD) ? 1 : 0;
+        val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(),
+                        gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(flag));
+        flag = (data &
+                NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST) ? 1 : 0;
+        val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(),
+                        gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(flag));
+        gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val);
+}
+
 
 static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data)
 {
@@ -1120,6 +1145,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr,
                 case NVC097_SET_COALESCE_BUFFER_SIZE:
                         gr_gv11b_set_coalesce_buffer_size(g, data);
                         break;
+                case NVC397_SET_TEX_IN_DBG:
+                        gr_gv11b_set_tex_in_dbg(g, data);
+                        break;
                 default:
                         goto fail;
                 }