diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-12-15 12:04:15 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-17 15:29:09 -0500 |
commit | 2f6698b863c9cc1db6455637b7c72e812b470b93 (patch) | |
tree | d0c8abf32d6994b9f54bf5eddafd8316e038c829 /drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |
parent | 6a73114788ffafe4c53771c707ecbd9c9ea0a117 (diff) |
gpu: nvgpu: Make graphics context property of TSG
Move graphics context ownership to TSG instead of channel. Combine
channel_ctx_gk20a and gr_ctx_desc to one structure, because the split
between them was arbitrary. Move context header to be property of
channel.
Bug 1842197
Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1639532
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 66 |
1 files changed, 42 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d5924169..3030def8 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1373,7 +1373,7 @@ fail_free: | |||
1373 | } | 1373 | } |
1374 | 1374 | ||
1375 | int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, | 1375 | int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, |
1376 | struct gr_ctx_desc *gr_ctx, | 1376 | struct nvgpu_gr_ctx *gr_ctx, |
1377 | struct vm_gk20a *vm, u32 class, | 1377 | struct vm_gk20a *vm, u32 class, |
1378 | u32 graphics_preempt_mode, | 1378 | u32 graphics_preempt_mode, |
1379 | u32 compute_preempt_mode) | 1379 | u32 compute_preempt_mode) |
@@ -1497,13 +1497,13 @@ fail: | |||
1497 | } | 1497 | } |
1498 | 1498 | ||
1499 | void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | 1499 | void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, |
1500 | struct channel_ctx_gk20a *ch_ctx, | 1500 | struct channel_gk20a *c, |
1501 | struct nvgpu_mem *mem) | 1501 | struct nvgpu_mem *mem) |
1502 | { | 1502 | { |
1503 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; | 1503 | struct tsg_gk20a *tsg; |
1504 | struct ctx_header_desc *ctx = &ch_ctx->ctx_header; | 1504 | struct nvgpu_gr_ctx *gr_ctx; |
1505 | struct ctx_header_desc *ctx = &c->ctx_header; | ||
1505 | struct nvgpu_mem *ctxheader = &ctx->mem; | 1506 | struct nvgpu_mem *ctxheader = &ctx->mem; |
1506 | |||
1507 | u32 gfxp_preempt_option = | 1507 | u32 gfxp_preempt_option = |
1508 | ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); | 1508 | ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); |
1509 | u32 cilp_preempt_option = | 1509 | u32 cilp_preempt_option = |
@@ -1514,6 +1514,12 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1514 | 1514 | ||
1515 | gk20a_dbg_fn(""); | 1515 | gk20a_dbg_fn(""); |
1516 | 1516 | ||
1517 | tsg = tsg_gk20a_from_ch(c); | ||
1518 | if (!tsg) | ||
1519 | return; | ||
1520 | |||
1521 | gr_ctx = &tsg->gr_ctx; | ||
1522 | |||
1517 | if (gr_ctx->graphics_preempt_mode == | 1523 | if (gr_ctx->graphics_preempt_mode == |
1518 | NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) { | 1524 | NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) { |
1519 | gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); | 1525 | gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); |
@@ -1552,7 +1558,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1552 | gr_ctx->preempt_ctxsw_buffer.gpu_va); | 1558 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1553 | } | 1559 | } |
1554 | 1560 | ||
1555 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true); | 1561 | err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, true); |
1556 | if (err) { | 1562 | if (err) { |
1557 | nvgpu_err(g, "can't map patch context"); | 1563 | nvgpu_err(g, "can't map patch context"); |
1558 | goto out; | 1564 | goto out; |
@@ -1564,7 +1570,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1564 | (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); | 1570 | (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); |
1565 | 1571 | ||
1566 | gk20a_dbg_info("attrib cb addr : 0x%016x", addr); | 1572 | gk20a_dbg_info("attrib cb addr : 0x%016x", addr); |
1567 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); | 1573 | g->ops.gr.commit_global_attrib_cb(g, gr_ctx, addr, true); |
1568 | 1574 | ||
1569 | addr = (u64_lo32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) >> | 1575 | addr = (u64_lo32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) >> |
1570 | gr_scc_pagepool_base_addr_39_8_align_bits_v()) | | 1576 | gr_scc_pagepool_base_addr_39_8_align_bits_v()) | |
@@ -1575,7 +1581,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1575 | if (size == g->ops.gr.pagepool_default_size(g)) | 1581 | if (size == g->ops.gr.pagepool_default_size(g)) |
1576 | size = gr_scc_pagepool_total_pages_hwmax_v(); | 1582 | size = gr_scc_pagepool_total_pages_hwmax_v(); |
1577 | 1583 | ||
1578 | g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); | 1584 | g->ops.gr.commit_global_pagepool(g, gr_ctx, addr, size, true); |
1579 | 1585 | ||
1580 | addr = (u64_lo32(gr_ctx->spill_ctxsw_buffer.gpu_va) >> | 1586 | addr = (u64_lo32(gr_ctx->spill_ctxsw_buffer.gpu_va) >> |
1581 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | | 1587 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | |
@@ -1584,28 +1590,28 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1584 | size = gr_ctx->spill_ctxsw_buffer.size / | 1590 | size = gr_ctx->spill_ctxsw_buffer.size / |
1585 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); | 1591 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); |
1586 | 1592 | ||
1587 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1593 | gr_gk20a_ctx_patch_write(g, gr_ctx, |
1588 | gr_gpc0_swdx_rm_spill_buffer_addr_r(), | 1594 | gr_gpc0_swdx_rm_spill_buffer_addr_r(), |
1589 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr), | 1595 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr), |
1590 | true); | 1596 | true); |
1591 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1597 | gr_gk20a_ctx_patch_write(g, gr_ctx, |
1592 | gr_gpc0_swdx_rm_spill_buffer_size_r(), | 1598 | gr_gpc0_swdx_rm_spill_buffer_size_r(), |
1593 | gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), | 1599 | gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), |
1594 | true); | 1600 | true); |
1595 | 1601 | ||
1596 | cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); | 1602 | cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); |
1597 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1603 | gr_gk20a_ctx_patch_write(g, gr_ctx, |
1598 | gr_gpcs_swdx_beta_cb_ctrl_r(), | 1604 | gr_gpcs_swdx_beta_cb_ctrl_r(), |
1599 | gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f( | 1605 | gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f( |
1600 | cbes_reserve), | 1606 | cbes_reserve), |
1601 | true); | 1607 | true); |
1602 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1608 | gr_gk20a_ctx_patch_write(g, gr_ctx, |
1603 | gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(), | 1609 | gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(), |
1604 | gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f( | 1610 | gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f( |
1605 | cbes_reserve), | 1611 | cbes_reserve), |
1606 | true); | 1612 | true); |
1607 | 1613 | ||
1608 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, true); | 1614 | gr_gk20a_ctx_patch_write_end(g, gr_ctx, true); |
1609 | } | 1615 | } |
1610 | 1616 | ||
1611 | out: | 1617 | out: |
@@ -1902,10 +1908,9 @@ int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, | |||
1902 | } | 1908 | } |
1903 | 1909 | ||
1904 | void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | 1910 | void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, |
1905 | struct channel_ctx_gk20a *ch_ctx, | 1911 | struct nvgpu_gr_ctx *gr_ctx, |
1906 | u64 addr, bool patch) | 1912 | u64 addr, bool patch) |
1907 | { | 1913 | { |
1908 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; | ||
1909 | int attrBufferSize; | 1914 | int attrBufferSize; |
1910 | 1915 | ||
1911 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) | 1916 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) |
@@ -1915,16 +1920,16 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | |||
1915 | 1920 | ||
1916 | attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); | 1921 | attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); |
1917 | 1922 | ||
1918 | gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch); | 1923 | gr_gm20b_commit_global_attrib_cb(g, gr_ctx, addr, patch); |
1919 | 1924 | ||
1920 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(), | 1925 | gr_gk20a_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(), |
1921 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) | | 1926 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) | |
1922 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); | 1927 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); |
1923 | 1928 | ||
1924 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(), | 1929 | gr_gk20a_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(), |
1925 | gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch); | 1930 | gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch); |
1926 | 1931 | ||
1927 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(), | 1932 | gr_gk20a_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(), |
1928 | gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) | | 1933 | gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) | |
1929 | gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); | 1934 | gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); |
1930 | } | 1935 | } |
@@ -2042,6 +2047,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
2042 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + | 2047 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + |
2043 | gk20a_gr_tpc_offset(g, tpc) + | 2048 | gk20a_gr_tpc_offset(g, tpc) + |
2044 | gv11b_gr_sm_offset(g, sm); | 2049 | gv11b_gr_sm_offset(g, sm); |
2050 | struct tsg_gk20a *tsg; | ||
2045 | 2051 | ||
2046 | *early_exit = false; | 2052 | *early_exit = false; |
2047 | *ignore_debugger = false; | 2053 | *ignore_debugger = false; |
@@ -2054,9 +2060,14 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
2054 | return gr_gv11b_handle_warp_esr_error_mmu_nack(g, gpc, tpc, sm, | 2060 | return gr_gv11b_handle_warp_esr_error_mmu_nack(g, gpc, tpc, sm, |
2055 | warp_esr, fault_ch); | 2061 | warp_esr, fault_ch); |
2056 | 2062 | ||
2057 | if (fault_ch) | 2063 | if (fault_ch) { |
2058 | cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == | 2064 | tsg = tsg_gk20a_from_ch(fault_ch); |
2065 | if (!tsg) | ||
2066 | return -EINVAL; | ||
2067 | |||
2068 | cilp_enabled = (tsg->gr_ctx.compute_preempt_mode == | ||
2059 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP); | 2069 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP); |
2070 | } | ||
2060 | 2071 | ||
2061 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 2072 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
2062 | "SM Exception received on gpc %d tpc %d sm %d = 0x%08x", | 2073 | "SM Exception received on gpc %d tpc %d sm %d = 0x%08x", |
@@ -2509,7 +2520,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2509 | if (err) | 2520 | if (err) |
2510 | return err; | 2521 | return err; |
2511 | 2522 | ||
2512 | ctx = &c->ch_ctx.ctx_header; | 2523 | ctx = &c->ctx_header; |
2513 | addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); | 2524 | addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); |
2514 | addr_hi = u64_hi32(ctx->mem.gpu_va); | 2525 | addr_hi = u64_hi32(ctx->mem.gpu_va); |
2515 | 2526 | ||
@@ -2529,7 +2540,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2529 | 2540 | ||
2530 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) | 2541 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) |
2531 | { | 2542 | { |
2532 | struct channel_ctx_gk20a *ch_ctx = NULL; | 2543 | struct nvgpu_gr_ctx *ch_ctx = NULL; |
2533 | u32 pd_ab_dist_cfg0; | 2544 | u32 pd_ab_dist_cfg0; |
2534 | u32 ds_debug; | 2545 | u32 ds_debug; |
2535 | u32 mpc_vtg_debug; | 2546 | u32 mpc_vtg_debug; |
@@ -2836,11 +2847,18 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
2836 | struct channel_gk20a *ch, u32 sm_id, | 2847 | struct channel_gk20a *ch, u32 sm_id, |
2837 | struct nvgpu_gr_sm_error_state *sm_error_state) | 2848 | struct nvgpu_gr_sm_error_state *sm_error_state) |
2838 | { | 2849 | { |
2850 | struct tsg_gk20a *tsg; | ||
2839 | u32 gpc, tpc, sm, offset; | 2851 | u32 gpc, tpc, sm, offset; |
2840 | struct gr_gk20a *gr = &g->gr; | 2852 | struct gr_gk20a *gr = &g->gr; |
2841 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | 2853 | struct nvgpu_gr_ctx *ch_ctx; |
2842 | int err = 0; | 2854 | int err = 0; |
2843 | 2855 | ||
2856 | tsg = tsg_gk20a_from_ch(ch); | ||
2857 | if (!tsg) | ||
2858 | return -EINVAL; | ||
2859 | |||
2860 | ch_ctx = &tsg->gr_ctx; | ||
2861 | |||
2844 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 2862 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
2845 | 2863 | ||
2846 | gr->sm_error_states[sm_id].hww_global_esr = | 2864 | gr->sm_error_states[sm_id].hww_global_esr = |