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authorPeter Daifuku <pdaifuku@nvidia.com>2017-11-08 21:32:26 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-13 21:19:28 -0500
commit0f5202368781c5398e3d026dc408d79a37ad5aed (patch)
tree95a114420e9eb03e678998e354c2efac8e69d87a /drivers/gpu/nvgpu/gv11b/gr_gv11b.c
parentd64241cb5a0ca21ae2c88419d34ad79715a4588a (diff)
gpu: nvgpu: ctx_patch_write fixes
- Update commit_global_timeslice to remove unused patch parameter - Update calls to ctx_patch_write_begin/end to add update_patch_count param JIRA ESRM-74 Bug 2012077 Change-Id: Ie2e640dfa0ab7193a062a58f588575f220e5efd3 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594791 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c29
1 files changed, 8 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 4da2ef59..3a3406f9 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -2214,8 +2214,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
2214 2214
2215 2215
2216 2216
2217int gr_gv11b_commit_global_timeslice(struct gk20a *g, 2217int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c)
2218 struct channel_gk20a *c, bool patch)
2219{ 2218{
2220 struct channel_ctx_gk20a *ch_ctx = NULL; 2219 struct channel_ctx_gk20a *ch_ctx = NULL;
2221 u32 pd_ab_dist_cfg0; 2220 u32 pd_ab_dist_cfg0;
@@ -2230,15 +2229,6 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g,
2230 ds_debug = gk20a_readl(g, gr_ds_debug_r()); 2229 ds_debug = gk20a_readl(g, gr_ds_debug_r());
2231 mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); 2230 mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r());
2232 2231
2233 if (patch) {
2234 int err;
2235
2236 ch_ctx = &c->ch_ctx;
2237 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
2238 if (err)
2239 return err;
2240 }
2241
2242 pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); 2232 pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r());
2243 pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); 2233 pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r());
2244 2234
@@ -2252,17 +2242,14 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g,
2252 mpc_vtg_debug; 2242 mpc_vtg_debug;
2253 2243
2254 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, 2244 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf,
2255 patch); 2245 false);
2256 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), 2246 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(),
2257 pe_vsc_vpc, patch); 2247 pe_vsc_vpc, false);
2258 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(), 2248 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(),
2259 pd_ab_dist_cfg0, patch); 2249 pd_ab_dist_cfg0, false);
2260 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, patch); 2250 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, false);
2261 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), 2251 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(),
2262 mpc_vtg_debug, patch); 2252 mpc_vtg_debug, false);
2263
2264 if (patch)
2265 gr_gk20a_ctx_patch_write_end(g, ch_ctx);
2266 2253
2267 return 0; 2254 return 0;
2268} 2255}
@@ -2568,7 +2555,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g,
2568 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, 2555 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset,
2569 gr->sm_error_states[sm_id].hww_warp_esr_report_mask); 2556 gr->sm_error_states[sm_id].hww_warp_esr_report_mask);
2570 } else { 2557 } else {
2571 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); 2558 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false);
2572 if (err) 2559 if (err)
2573 goto enable_ctxsw; 2560 goto enable_ctxsw;
2574 2561
@@ -2583,7 +2570,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g,
2583 gr->sm_error_states[sm_id].hww_warp_esr_report_mask, 2570 gr->sm_error_states[sm_id].hww_warp_esr_report_mask,
2584 true); 2571 true);
2585 2572
2586 gr_gk20a_ctx_patch_write_end(g, ch_ctx); 2573 gr_gk20a_ctx_patch_write_end(g, ch_ctx, false);
2587 } 2574 }
2588 2575
2589enable_ctxsw: 2576enable_ctxsw: