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authorDeepak Nibade <dnibade@nvidia.com>2018-01-16 06:07:37 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-02-07 18:35:47 -0500
commitf0cbe19b12524f5df6466eaf86acbfb349def6b1 (patch)
treebed8a312e29592d41d9de4afb331756c2d38fb96 /drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
parent0c8deb74aff6d0781cdf3278f56d7bce42b16a67 (diff)
gpu: nvgpu: add user API to get read-only syncpoint address map
Add User space API NVGPU_AS_IOCTL_GET_SYNC_RO_MAP to get read-only syncpoint address map in user space We already map whole syncpoint shim to each address space with base address being vm->syncpt_ro_map_gpu_va This new API exposes this base GPU_VA address of syncpoint map, and unit size of each syncpoint to user space. User space can then calculate address of each syncpoint as syncpoint_address = base_gpu_va + (syncpoint_id * syncpoint_unit_size) Note that this syncpoint address is read_only, and should be only used for inserting semaphore acquires. Adding semaphore release with this address would result in MMU_FAULT Define new HAL g->ops.fifo.get_sync_ro_map and set this for all GPUs supported on Xavier SoC Bug 200327559 Change-Id: Ica0db48fc28fdd0ff2a5eb09574dac843dc5e4fd Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1649365 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index fc1ddf83..c0e6e5cd 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B Fifo 2 * GV11B Fifo
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -102,6 +102,8 @@ int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
102 u32 syncpt_id, struct nvgpu_mem *syncpt_buf); 102 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
103void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, 103void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c,
104 struct nvgpu_mem *syncpt_buf); 104 struct nvgpu_mem *syncpt_buf);
105int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm,
106 u64 *base_gpuva, u32 *sync_size);
105void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, 107void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g,
106 struct priv_cmd_entry *cmd, u32 off, 108 struct priv_cmd_entry *cmd, u32 off,
107 u32 id, u32 thresh, u64 gpu_va_base); 109 u32 id, u32 thresh, u64 gpu_va_base);