gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo ops

Context TSG teardown procedure:

1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE.
   This enables SW to determine whether a context has hung later in the
   process: otherwise, ongoing work on the runlist may keep ENG_STATUS from
   reaching a steady state.

2. Disable all channels in the TSG being torn down or submit a new runlist
   that does not contain the TSG.  This is to prevent the TSG from being
   rescheduled once scheduling is reenabled in step 6.

3. Initiate a preempt of the engine by writing the bit associated with its
   runlist to NV_PFIFO_RUNLIST_PREEMPT.  This allows to begin the preempt
   process prior to doing the slow register reads needed to determine
   whether the context has hit any interrupts or is hung.  Do not poll
   NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete.

4. Check for interrupts or hangs while waiting for the preempt to complete.
   During the pbdma/eng preempt finish polling, any stalling interrupts
   relating to runlist must be detected and handled in order for the
   preemption to complete.

5. If a reset is needed as determined by step 4:
  a. Halt the memory interface for the engine (as per the relevant engine
     procedure).
  b. Reset the engine via NV_PMC_ENABLE.
  c. Take the engine out of reset and reinit the engine (as per
     relevant engine procedure)
6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE.

JIRA GPUT19X-7

Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1327931
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
index 5b95ad9e..07a39da0 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
@@ -15,6 +15,9 @@
 
 #ifndef FIFO_GV11B_H
 #define FIFO_GV11B_H
+
+#define FIFO_INVAL_PBDMA_ID     ((u32)~0)
+
 struct gpu_ops;
 void gv11b_init_fifo(struct gpu_ops *gops);
 #endif