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authorseshendra Gadagottu <sgadagottu@nvidia.com>2017-12-05 19:14:37 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-18 13:30:24 -0500
commitf8402eb90a68ab1e38ef87166458dc064501a8f9 (patch)
treef8f17725209966fc23a3d985b10fc1553ef9b869 /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
parent2deab755e794ab14000a9f6549ee05ce0d0cdb2b (diff)
gpu: nvgpu: gv1xx: remove scg_type from channel info
scg_type for graphics_compute0 and compute1 is deprecated for gv1xx. Remove it from setting in the channel info. Bug 1842197 Change-Id: I37354adcd82bb0ab648e0f04d47de796b79f91cd Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640440 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c10
1 files changed, 2 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index a7a58e2f..7d3c5c75 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B fifo 2 * GV11B fifo
3 * 3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -184,13 +184,7 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
184 184
185 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); 185 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid));
186 186
187 if (c->t19x.subctx_id == CHANNEL_INFO_VEID0) 187 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
188 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
189 pbdma_set_channel_info_scg_type_graphics_compute0_f() |
190 pbdma_set_channel_info_veid_f(c->t19x.subctx_id));
191 else
192 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
193 pbdma_set_channel_info_scg_type_compute1_f() |
194 pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); 188 pbdma_set_channel_info_veid_f(c->t19x.subctx_id));
195 189
196 gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); 190 gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem);