gpu: nvgpu: add hal to mask/unmask intr during teardown

ctxsw timeout error prevents recovery as it can get triggered
periodically. Disable ctxsw timeout interrupt to allow recovery.

Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287

Change-Id: I47470e13968d8b26cdaf519b62fd510bc7ea05d9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019645
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry picked from commit 68c13e2f0447118d7391807c9b9269749d09a4ec
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2024899
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 31 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index b5af2972..5b84df47 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -982,6 +982,33 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g,
         }
 }
 
+void gv11b_fifo_teardown_mask_intr(struct gk20a *g)
+{
+        u32 val;
+
+        /*
+         * ctxsw timeout error prevents recovery, and ctxsw error will retrigger
+         * every 100ms. Disable ctxsw timeout error to allow recovery.
+         */
+        val = gk20a_readl(g, fifo_intr_en_0_r());
+        val &= ~ fifo_intr_0_ctxsw_timeout_pending_f();
+        gk20a_writel(g, fifo_intr_en_0_r(), val);
+        gk20a_writel(g, fifo_intr_ctxsw_timeout_r(),
+                        gk20a_readl(g, fifo_intr_ctxsw_timeout_r()));
+
+}
+
+void gv11b_fifo_teardown_unmask_intr(struct gk20a *g)
+{
+        u32 val;
+
+        /* enable ctxsw timeout interrupt */
+        val = gk20a_readl(g, fifo_intr_en_0_r());
+        val |= fifo_intr_0_ctxsw_timeout_pending_f();
+        gk20a_writel(g, fifo_intr_en_0_r(), val);
+}
+
+
 void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
                         u32 id, unsigned int id_type, unsigned int rc_type,
                          struct mmu_fault_info *mmfault)
@@ -1001,6 +1028,8 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
                         runlist_lock);
         }
 
+        g->ops.fifo.teardown_mask_intr(g);
+
         /* get runlist id and tsg */
         if (id_type == ID_TYPE_TSG) {
                 if (id != FIFO_INVAL_TSG_ID) {
@@ -1195,6 +1224,8 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
                 nvgpu_pmu_enable_elpg(g);
         }
 
+        g->ops.fifo.teardown_unmask_intr(g);
+
         /* release runlist_lock */
         if (runlist_id != FIFO_INVAL_RUNLIST_ID) {
                 nvgpu_log_fn(g, "release runlist_lock runlist_id = %d",