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author | Alex Waterman <alexw@nvidia.com> | 2018-03-01 23:47:25 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-03-03 01:10:14 -0500 |
commit | 89fbf39a05483917c0a9f3453fd94c724bc37375 (patch) | |
tree | 55fdd147c0a7eb80b8fc50ecd9f4b0c80f1322f1 /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |
parent | ef116a6e632522def7493921666c3241318ce100 (diff) |
Revert "Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working""
This reverts commit 5a35a95654d561fce09a3b9abf6b82bb7a29d74b.
JIRA EVLR-2333
Change-Id: I923c32496c343d39d34f6d406c38a9f6ce7dc6e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1667167
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index feed2002..9e60d9f7 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -101,12 +101,14 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) | |||
101 | c->runqueue_sel) | | 101 | c->runqueue_sel) | |
102 | ram_rl_entry_chan_userd_target_f( | 102 | ram_rl_entry_chan_userd_target_f( |
103 | nvgpu_aperture_mask(g, &g->fifo.userd, | 103 | nvgpu_aperture_mask(g, &g->fifo.userd, |
104 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), | 104 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), |
105 | ram_rl_entry_chan_userd_target_vid_mem_v())) | | 105 | ram_rl_entry_chan_userd_target_sys_mem_coh_v(), |
106 | ram_rl_entry_chan_userd_target_vid_mem_v())) | | ||
106 | ram_rl_entry_chan_inst_target_f( | 107 | ram_rl_entry_chan_inst_target_f( |
107 | nvgpu_aperture_mask(g, &c->inst_block, | 108 | nvgpu_aperture_mask(g, &c->inst_block, |
108 | ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), | 109 | ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), |
109 | ram_rl_entry_chan_inst_target_vid_mem_v())); | 110 | ram_rl_entry_chan_inst_target_sys_mem_coh_v(), |
111 | ram_rl_entry_chan_inst_target_vid_mem_v())); | ||
110 | 112 | ||
111 | addr_lo = u64_lo32(c->userd_iova) >> | 113 | addr_lo = u64_lo32(c->userd_iova) >> |
112 | ram_rl_entry_chan_userd_ptr_align_shift_v(); | 114 | ram_rl_entry_chan_userd_ptr_align_shift_v(); |