gpu: nvgpu: gv11b: Use nvgpu_rwsem as TSG channel lock

Use abstract nvgpu_rwsem as TSG channel list lock instead of the Linux
specific rw_semaphore.

JIRA NVGPU-259

Change-Id: I5f6c918464315e3d140bea0c61a619c3712619c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579934
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index e9830c0e..7bb3d654 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -545,11 +545,11 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg)
         struct gk20a *g = tsg->g;
         struct channel_gk20a *ch;
 
-        down_read(&tsg->ch_list_lock);
+        nvgpu_rwsem_down_read(&tsg->ch_list_lock);
         list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
                 gv11b_reset_eng_faulted_ch(g, ch->chid);
         }
-        up_read(&tsg->ch_list_lock);
+        nvgpu_rwsem_up_read(&tsg->ch_list_lock);
 }
 
 static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid)
@@ -566,11 +566,11 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg)
         struct gk20a *g = tsg->g;
         struct channel_gk20a *ch;
 
-        down_read(&tsg->ch_list_lock);
+        nvgpu_rwsem_down_read(&tsg->ch_list_lock);
         list_for_each_entry(ch, &tsg->ch_list, ch_entry) {
                 gv11b_reset_pbdma_faulted_ch(g, ch->chid);
         }
-        up_read(&tsg->ch_list_lock);
+        nvgpu_rwsem_up_read(&tsg->ch_list_lock);
 }
 
 void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g,
@@ -799,11 +799,11 @@ int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg)
         struct gk20a *g = tsg->g;
         struct channel_gk20a *ch;
 
-        down_read(&tsg->ch_list_lock);
+        nvgpu_rwsem_down_read(&tsg->ch_list_lock);
         nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
                 g->ops.fifo.enable_channel(ch);
         }
-        up_read(&tsg->ch_list_lock);
+        nvgpu_rwsem_up_read(&tsg->ch_list_lock);
 
         return 0;
 }