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authorRichard Zhao <rizhao@nvidia.com>2017-08-10 19:34:16 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-11 14:08:41 -0400
commit3197a918d5052c71ad854f6b22fdb35bfe7cebe2 (patch)
tree887f155d104926d38d74583739bacf57a57c040b /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
parentde8e057f7eebcfe676278826ab457bf86b1b36fd (diff)
gpu: nvgpu: gv11b: add max_subctx_count to g->fifo.t19x
- For better performance. It used to read register every time referencing max_subctx_count. - Avoid reading registers for vgpu. Jira VFND-3797 Change-Id: Id6e6b15a0d9a035795e8a9a2c6bb63524c5eb544 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537009 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index e210d40d..bd769f75 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -40,6 +40,7 @@
40#include <nvgpu/hw/gv11b/hw_top_gv11b.h> 40#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
41#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> 41#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
42#include <nvgpu/hw/gv11b/hw_mc_gv11b.h> 42#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
43#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
43 44
44#include "fifo_gv11b.h" 45#include "fifo_gv11b.h"
45#include "subctx_gv11b.h" 46#include "subctx_gv11b.h"
@@ -1717,16 +1718,20 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g)
1717 struct fifo_gk20a *f = &g->fifo; 1718 struct fifo_gk20a *f = &g->fifo;
1718 1719
1719 f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); 1720 f->t19x.usermode_regs = g->regs + usermode_cfg0_r();
1721 f->t19x.max_subctx_count =
1722 gr_pri_fe_chip_def_info_max_veid_count_v(
1723 gk20a_readl(g, gr_pri_fe_chip_def_info_r()));
1720 return 0; 1724 return 0;
1721} 1725}
1722 1726
1723static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, 1727static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id,
1724 u32 mmu_fault_id) 1728 u32 mmu_fault_id)
1725{ 1729{
1730 struct fifo_gk20a *f = &g->fifo;
1726 u32 num_subctx; 1731 u32 num_subctx;
1727 u32 veid = FIFO_INVAL_VEID; 1732 u32 veid = FIFO_INVAL_VEID;
1728 1733
1729 num_subctx = gv11b_get_max_subctx_count(g); 1734 num_subctx = f->t19x.max_subctx_count;
1730 1735
1731 if (mmu_fault_id >= gr_eng_fault_id && 1736 if (mmu_fault_id >= gr_eng_fault_id &&
1732 mmu_fault_id < (gr_eng_fault_id + num_subctx)) 1737 mmu_fault_id < (gr_eng_fault_id + num_subctx))