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author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-10-17 13:26:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-10-21 16:44:04 -0400 |
commit | 2fd1ee0ca784e4235766601d6a7ef52ba1f0c519 (patch) | |
tree | f1a01d1abf418d0f0a8a5d3fe58f3928c2bc13bc /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |
parent | 35d2db64e28df6d65fed381c793f0954eed5eb7b (diff) |
gpu: nvgpu: gv11b: update ramfc
Updated ramfc:
- To include channel veid info
- Set valid context bit
- Enabled userd writeback
JIRA GV11B-11
Change-Id: I0e8c62fe0dee02071b0ca60f157151038ab5c09b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1237764
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index c6e0f0a2..0e1c1999 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -24,6 +24,9 @@ | |||
24 | #include "hw_ccsr_gv11b.h" | 24 | #include "hw_ccsr_gv11b.h" |
25 | #include "hw_usermode_gv11b.h" | 25 | #include "hw_usermode_gv11b.h" |
26 | 26 | ||
27 | #define CHANNEL_INFO_VEID0 0 | ||
28 | #define PBDMA_SUBDEVICE_ID 1 | ||
29 | |||
27 | static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) | 30 | static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) |
28 | { | 31 | { |
29 | 32 | ||
@@ -82,6 +85,88 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) | |||
82 | runlist[0], runlist[1], runlist[2], runlist[3]); | 85 | runlist[0], runlist[1], runlist[2], runlist[3]); |
83 | } | 86 | } |
84 | 87 | ||
88 | static void gv11b_userd_writeback_config(struct gk20a *g) | ||
89 | { | ||
90 | gk20a_writel(g, fifo_userd_writeback_r(), fifo_userd_writeback_timer_f( | ||
91 | fifo_userd_writeback_timer_100us_v())); | ||
92 | |||
93 | |||
94 | } | ||
95 | |||
96 | static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, | ||
97 | u64 gpfifo_base, u32 gpfifo_entries, u32 flags) | ||
98 | { | ||
99 | struct gk20a *g = c->g; | ||
100 | struct mem_desc *mem = &c->inst_block; | ||
101 | u32 data; | ||
102 | |||
103 | gk20a_dbg_fn(""); | ||
104 | |||
105 | gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); | ||
106 | |||
107 | gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), | ||
108 | pbdma_gp_base_offset_f( | ||
109 | u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); | ||
110 | |||
111 | gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), | ||
112 | pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | | ||
113 | pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); | ||
114 | |||
115 | gk20a_mem_wr32(g, mem, ram_fc_signature_w(), | ||
116 | c->g->ops.fifo.get_pbdma_signature(c->g)); | ||
117 | |||
118 | gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), | ||
119 | pbdma_pb_header_priv_user_f() | | ||
120 | pbdma_pb_header_method_zero_f() | | ||
121 | pbdma_pb_header_subchannel_zero_f() | | ||
122 | pbdma_pb_header_level_main_f() | | ||
123 | pbdma_pb_header_first_true_f() | | ||
124 | pbdma_pb_header_type_inc_f()); | ||
125 | |||
126 | gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), | ||
127 | pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) | | ||
128 | pbdma_subdevice_status_active_f() | | ||
129 | pbdma_subdevice_channel_dma_enable_f()); | ||
130 | |||
131 | gk20a_mem_wr32(g, mem, ram_fc_target_w(), | ||
132 | pbdma_target_eng_ctx_valid_true_f() | | ||
133 | pbdma_target_engine_sw_f()); | ||
134 | |||
135 | gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), | ||
136 | channel_gk20a_pbdma_acquire_val(c)); | ||
137 | |||
138 | gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), | ||
139 | pbdma_runlist_timeslice_timeout_128_f() | | ||
140 | pbdma_runlist_timeslice_timescale_3_f() | | ||
141 | pbdma_runlist_timeslice_enable_true_f()); | ||
142 | |||
143 | |||
144 | gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); | ||
145 | |||
146 | /* Until full subcontext is supported, always use VEID0 */ | ||
147 | gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(), | ||
148 | pbdma_set_channel_info_scg_type_graphics_compute0_f() | | ||
149 | pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); | ||
150 | |||
151 | if (c->is_privileged_channel) { | ||
152 | /* Set privilege level for channel */ | ||
153 | gk20a_mem_wr32(g, mem, ram_fc_config_w(), | ||
154 | pbdma_config_auth_level_privileged_f()); | ||
155 | |||
156 | gk20a_channel_setup_ramfc_for_privileged_channel(c); | ||
157 | } | ||
158 | |||
159 | /* Enable userd writeback */ | ||
160 | data = gk20a_mem_rd32(g, mem, ram_fc_config_w()); | ||
161 | data = data | pbdma_config_userd_writeback_enable_f(); | ||
162 | gk20a_mem_wr32(g, mem, ram_fc_config_w(),data); | ||
163 | |||
164 | gv11b_userd_writeback_config(g); | ||
165 | |||
166 | return channel_gp10b_commit_userd(c); | ||
167 | } | ||
168 | |||
169 | |||
85 | static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) | 170 | static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) |
86 | { | 171 | { |
87 | gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); | 172 | gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); |
@@ -131,4 +216,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) | |||
131 | gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; | 216 | gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; |
132 | gops->fifo.userd_gp_get = gv11b_userd_gp_get; | 217 | gops->fifo.userd_gp_get = gv11b_userd_gp_get; |
133 | gops->fifo.userd_gp_put = gv11b_userd_gp_put; | 218 | gops->fifo.userd_gp_put = gv11b_userd_gp_put; |
219 | gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; | ||
134 | } | 220 | } |