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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-07-06 11:50:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-09 17:40:50 -0400
commit0ddd219697155bcb64aaa04544108519686e16cc (patch)
treee33da070ae0a486bca5e0510b2c5a24915d16187 /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
parentbbebc611bc10a824d5d51fc2ea9d0408e350d26a (diff)
gpu: nvgpu: Conditional enable for replayable fault
Enable replayable fault only for contexts where they are requested. This required moving the code to initialize subcontexts to happen later. Fix signedness issues in definition of flags. JIRA NVGPU-714 Change-Id: I472004e13b1ea46c1bd202f9b12d2ce221b756f9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773262 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 75ff9525..4edaaac1 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -138,11 +138,17 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
138 struct gk20a *g = c->g; 138 struct gk20a *g = c->g;
139 struct nvgpu_mem *mem = &c->inst_block; 139 struct nvgpu_mem *mem = &c->inst_block;
140 u32 data; 140 u32 data;
141 bool replayable = false;
141 142
142 nvgpu_log_fn(g, " "); 143 nvgpu_log_fn(g, " ");
143 144
144 nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); 145 nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
145 146
147 if ((flags & NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0) {
148 replayable = true;
149 }
150 gv11b_init_subcontext_pdb(c->vm, mem, replayable);
151
146 nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), 152 nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
147 pbdma_gp_base_offset_f( 153 pbdma_gp_base_offset_f(
148 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); 154 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));