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author | Thomas Fleury <tfleury@nvidia.com> | 2018-01-23 17:20:43 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-26 00:48:24 -0500 |
commit | 0601fd25a5e01d0da638efef13c58b64f198bafb (patch) | |
tree | dbe843912a525497103bbe9beefc6e78ff67c8c9 /drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |
parent | 223ea4d8a179835dd5899bbc12fe78b4998b0bd7 (diff) |
gpu: nvgpu: gv100: nvlink endpoint driver
The following changes implements the initial (as per bringup) nvlink driver.
(1) SW initialization of nvlink core driver structures
(2) Nvlink interrupt handling
(3) Device initialization (IOCTRL, pll and clocks, device level intr)
(4) Falcon support for minion
(5) Minion load and bootstrapping
(6) Link initialization and DL PROD settings
(7) Device Interface init (and switching HSHUB to nvlink)
(8) HS set/get mode for both link and sublink
(9) Topology discovery and VBIOS settings.
(10) Ensures we get physical contiguous memory when Nvlink is enabled
This driver includes a hack for the current single dev/single link limitation.
JIRA: EVLR-2331
JIRA: EVLR-2330
JIRA: EVLR-2329
JIRA: EVLR-2328
Change-Id: Idca9a819179376cc655784482b24b575a52fa9e5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656790
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 89f3f0b9..97ab7aab 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -482,7 +482,7 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, | |||
482 | eng_stat = gk20a_readl(g, fifo_engine_status_r(act_eng_id)); | 482 | eng_stat = gk20a_readl(g, fifo_engine_status_r(act_eng_id)); |
483 | ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); | 483 | ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); |
484 | 484 | ||
485 | if (gv11b_mc_is_stall_and_eng_intr_pending(g, act_eng_id)) { | 485 | if (g->ops.mc.is_stall_and_eng_intr_pending(g, act_eng_id)) { |
486 | stall_intr = true; | 486 | stall_intr = true; |
487 | nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, | 487 | nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, |
488 | "stall intr set, " | 488 | "stall intr set, " |