diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-01-17 15:39:13 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-23 01:20:15 -0500 |
commit | f3f14cdff53f4b936e2505d44aad6e3bca143056 (patch) | |
tree | 8d6438132b8ca429758d18142c5f569f60f2bc35 /drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |
parent | 193a2ed38ca51d898ac811820ab86237c84e18eb (diff) |
gpu: nvgpu: Fold T19x code back to main code paths
Lots of code paths were split to T19x specific code paths and structs
due to split repository. Now that repositories are merged, fold all of
them back to main code paths and structs and remove the T19x specific
Kconfig flag.
Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640606
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/fb_gv11b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 8ac3cb7b..b7a0a3cf 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B FB | 2 | * GV11B FB |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -568,9 +568,9 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
568 | uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); | 568 | uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); |
569 | 569 | ||
570 | 570 | ||
571 | g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0] += | 571 | g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0] += |
572 | corrected_delta; | 572 | corrected_delta; |
573 | g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0] += | 573 | g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0] += |
574 | uncorrected_delta; | 574 | uncorrected_delta; |
575 | 575 | ||
576 | if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) | 576 | if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) |
@@ -584,8 +584,8 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
584 | "ecc error address: 0x%x", ecc_addr); | 584 | "ecc error address: 0x%x", ecc_addr); |
585 | nvgpu_log(g, gpu_dbg_intr, | 585 | nvgpu_log(g, gpu_dbg_intr, |
586 | "ecc error count corrected: %d, uncorrected %d", | 586 | "ecc error count corrected: %d, uncorrected %d", |
587 | g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0], | 587 | g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0], |
588 | g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0]); | 588 | g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0]); |
589 | } | 589 | } |
590 | 590 | ||
591 | static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) | 591 | static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) |
@@ -626,9 +626,9 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
626 | uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); | 626 | uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); |
627 | 627 | ||
628 | 628 | ||
629 | g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0] += | 629 | g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0] += |
630 | corrected_delta; | 630 | corrected_delta; |
631 | g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0] += | 631 | g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0] += |
632 | uncorrected_delta; | 632 | uncorrected_delta; |
633 | 633 | ||
634 | if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) | 634 | if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) |
@@ -642,8 +642,8 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
642 | "ecc error address: 0x%x", ecc_addr); | 642 | "ecc error address: 0x%x", ecc_addr); |
643 | nvgpu_log(g, gpu_dbg_intr, | 643 | nvgpu_log(g, gpu_dbg_intr, |
644 | "ecc error count corrected: %d, uncorrected %d", | 644 | "ecc error count corrected: %d, uncorrected %d", |
645 | g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0], | 645 | g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0], |
646 | g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0]); | 646 | g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0]); |
647 | } | 647 | } |
648 | 648 | ||
649 | static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) | 649 | static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) |
@@ -684,9 +684,9 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
684 | uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); | 684 | uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); |
685 | 685 | ||
686 | 686 | ||
687 | g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0] += | 687 | g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0] += |
688 | corrected_delta; | 688 | corrected_delta; |
689 | g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0] += | 689 | g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0] += |
690 | uncorrected_delta; | 690 | uncorrected_delta; |
691 | 691 | ||
692 | if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) | 692 | if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) |
@@ -705,8 +705,8 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
705 | "ecc error address: 0x%x", ecc_addr); | 705 | "ecc error address: 0x%x", ecc_addr); |
706 | nvgpu_log(g, gpu_dbg_intr, | 706 | nvgpu_log(g, gpu_dbg_intr, |
707 | "ecc error count corrected: %d, uncorrected %d", | 707 | "ecc error count corrected: %d, uncorrected %d", |
708 | g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0], | 708 | g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0], |
709 | g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]); | 709 | g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0]); |
710 | } | 710 | } |
711 | 711 | ||
712 | static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) | 712 | static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) |