gpu: nvgpu: gv11b: add mmu fault handling

HUB reports following memory sub-system interrupts:
a) ACCESS_COUNTER_NOTIFY:
   GET != PUT for access counter notify buffer
b) ACCESS_COUNTER_ERROR:
   HUB received a NACK (BAR2 fault) when writing the
   notify buffer out to memory
c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY:
   Uncorrected ECC error detected by HUB MMU
d) MMU_REPLAYABLE_FAULT_NOTIFY:
   GET != PUT for replayable fault buffer
e) MMU_REPLAYABLE_FAULT_OVERFLOW:
   Overflow when writing to the replayable fault buffer
f) MMU_NONREPLAYABLE_FAULT_NOTIFY:
   GET != PUT for non-replayable fault buffer
g) MMU_NONREPLAYABLE_FAULT_OVERFLOW:
   Overflow when writing to the non-replayable fault buffer
h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU

This change is to :
-Detect other fault notify
-Copy fault info from fault snap register for other fault notify
 interrupt
-Detect and handle nonreplay/replay fault notify and fault overflow
-Copy fault info from fault buffer for nonreplay/replay fault
-Print fault info

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1493394
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 20 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
index 0bbd05b6..af87f990 100644
--- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
@@ -26,6 +26,7 @@
 #include "ce_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_ce_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 
 static u32 gv11b_ce_get_num_pce(struct gk20a *g)
 {
@@ -74,6 +75,25 @@ static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
         gp10b_ce_isr(g, inst_id, pri_base);
 }
 
+void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g)
+{
+        u32 reg_val, num_lce, lce, clear_intr;
+
+        reg_val = gk20a_readl(g, top_num_ces_r());
+        num_lce = top_num_ces_value_v(reg_val);
+        nvgpu_log_info(g, "num LCE: %d", num_lce);
+
+        for (lce = 0; lce < num_lce; lce++) {
+                reg_val = gk20a_readl(g, ce_intr_status_r(lce));
+                if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) {
+                        nvgpu_log(g, gpu_dbg_intr,
+                        "ce: lce %d: mthd buffer fault", lce);
+                        clear_intr = ce_intr_status_mthd_buffer_fault_reset_f();
+                        gk20a_writel(g, ce_intr_status_r(lce), clear_intr);
+                }
+        }
+}
+
 void gv11b_init_ce(struct gpu_ops *gops)
 {
         gp10b_init_ce(gops);