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authorseshendra Gadagottu <sgadagottu@nvidia.com>2018-02-28 20:56:34 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-13 17:09:16 -0400
commita5364c30b1298aec1f2c9f89aee7d94a31619c19 (patch)
tree0772337389ef979bb4c8982840a4950f7d43f59a /drivers/gpu/nvgpu/gv11b/acr_gv11b.c
parent4826bddfc40506b72378b6eed6ca5b86fbdf1a7f (diff)
gpu: nvgpu: gv11b: pmu: add dma coherent support
Setup pmu apertures based on dma coherent property. Bug 200394053 Change-Id: I45beff671e4b8741f2b1ffbc811618b074772ea0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1641609 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b/acr_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/gv11b/acr_gv11b.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
index 4fa3f324..7ca8c703 100644
--- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c
@@ -29,8 +29,8 @@
29#include <nvgpu/nvgpu_mem.h> 29#include <nvgpu/nvgpu_mem.h>
30#include <nvgpu/firmware.h> 30#include <nvgpu/firmware.h>
31#include <nvgpu/mm.h> 31#include <nvgpu/mm.h>
32#include <nvgpu/enabled.h>
33#include <nvgpu/acr/nvgpu_acr.h> 32#include <nvgpu/acr/nvgpu_acr.h>
33#include <nvgpu/enabled.h>
34 34
35#include "gk20a/gk20a.h" 35#include "gk20a/gk20a.h"
36#include "acr_gv11b.h" 36#include "acr_gv11b.h"
@@ -248,16 +248,25 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu,
248 248
249void gv11b_setup_apertures(struct gk20a *g) 249void gv11b_setup_apertures(struct gk20a *g)
250{ 250{
251 struct mm_gk20a *mm = &g->mm;
252 struct nvgpu_mem *inst_block = &mm->pmu.inst_block;
253
251 /* setup apertures - virtual */ 254 /* setup apertures - virtual */
252 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), 255 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
253 pwr_fbif_transcfg_mem_type_physical_f() | 256 pwr_fbif_transcfg_mem_type_physical_f() |
254 pwr_fbif_transcfg_target_noncoherent_sysmem_f()); 257 nvgpu_aperture_mask(g, inst_block,
258 pwr_fbif_transcfg_target_noncoherent_sysmem_f(),
259 pwr_fbif_transcfg_target_coherent_sysmem_f(),
260 pwr_fbif_transcfg_target_local_fb_f()));
255 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), 261 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
256 pwr_fbif_transcfg_mem_type_virtual_f()); 262 pwr_fbif_transcfg_mem_type_virtual_f());
257 /* setup apertures - physical */ 263 /* setup apertures - physical */
258 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), 264 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
259 pwr_fbif_transcfg_mem_type_physical_f() | 265 pwr_fbif_transcfg_mem_type_physical_f() |
260 pwr_fbif_transcfg_target_noncoherent_sysmem_f()); 266 nvgpu_aperture_mask(g, inst_block,
267 pwr_fbif_transcfg_target_noncoherent_sysmem_f(),
268 pwr_fbif_transcfg_target_coherent_sysmem_f(),
269 pwr_fbif_transcfg_target_local_fb_f()));
261 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), 270 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
262 pwr_fbif_transcfg_mem_type_physical_f() | 271 pwr_fbif_transcfg_mem_type_physical_f() |
263 pwr_fbif_transcfg_target_coherent_sysmem_f()); 272 pwr_fbif_transcfg_target_coherent_sysmem_f());